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VLSi

  1. 1. VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4Mani SrivastavaUCLA - EE Departmentmbs@ ee.ucla.edu
  2. 2. 2 Copyright 2001 © Mani Srivastava Reading for this Lecture Chapter 11 of Rabaey’s book
  3. 3. 3 Copyright 2001 © Mani Srivastava Four Phases in Creating a Chip This Future Lecture Lecture Previous Lecture
  4. 4. 4 Copyright 2001 © Mani Srivastava The Design Problem Source: sematech97 A growing gap between design complexity and design productivity [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  5. 5. 5 Copyright 2001 © Mani Srivastava Profound Impact on the way VLSI is Designed The old way: manual transistor twiddling expert “layout designers” entire chip hand-crafted okay for small chips… but cannot design billion transistor chips in this fashion The new way: using CAD tools at high level tools do the grunge work… high levels of abstractions – synthesis from a description of the behavior libraries of reusable cores, modules, and cells Chip design increasingly like object-oriented software design! [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  6. 6. 6 Copyright 2001 © Mani Srivastava Designing a VLSI Economic viability affected by design time Design time affected by the efficiency of concept → requirements → architecture → logic/memory → circuit → layout Continuous trade-off between performance (speed, area, power) size of die (hence cost of die and packaging) time of design (hence cost of engineering & schedule) ease of test generation and testability
  7. 7. 7 Copyright 2001 © Mani Srivastava VLSI-design Tools & Methodologies Goal is to reduce complexity, increase productivity, and increase chances of a working chip Key is the use of Constraints and Abstractions Constraints – help automate the procedure by simplifying the problem Abstractions – collapse detail and arrive at a simpler problem to deal with Different design methodologies different types of constraints and trade-offs choice driven by economics!
  8. 8. 8 Copyright 2001 © Mani Srivastava Design Domains Behavioral what a system does Structural how entities are connected together to perform the behavior Physical (geometrical) how to build a structure that has the required connectivity to implement the prescribed behavior
  9. 9. 9 Copyright 2001 © Mani Srivastava Levels of Design Abstractions for Each Design Domain Architectural Algorithmic Module or functional block Logical Switch Circuit Device etc.
  10. 10. 10 Copyright 2001 © Mani Srivastava Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S D n+ n+ [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  11. 11. 11 Copyright 2001 © Mani Srivastava Design Methodology Design process traverses iteratively between behavior, structure, and geometry abstractions CAD tools providing more and more automation
  12. 12. 12 Copyright 2001 © Mani Srivastava A More Simplified Flow
  13. 13. 13 Copyright 2001 © Mani Srivastava Principles of Structured Design Techniques Hierarchy Regularity Modularity Locality
  14. 14. 14 Copyright 2001 © Mani Srivastava Hierarchy Divide and conquer compose system from simpler widgets Analogy with software break large programs into threads and subroutines Hierarchy can be there in all domains behavior, structural, physical The hierarchy in different domains may not correspond e.g. a structural hierarchy may not map well to physical
  15. 15. 15 Copyright 2001 © Mani Srivastava Example of Structural Hierarchy
  16. 16. 16 Copyright 2001 © Mani Srivastava Example of Physical Hierarchy
  17. 17. 17 Copyright 2001 © Mani Srivastava Example of Structural Hierarchy
  18. 18. 18 Copyright 2001 © Mani Srivastava Example of Physical Hierarchy
  19. 19. 19 Copyright 2001 © Mani Srivastava Repartitioning Structural Hierarchy to Fit Physical Hierarchy
  20. 20. 20 Copyright 2001 © Mani Srivastava Regularity Hierarchy breaks a system into submodules but this may not solve the complexity problem there may not be any regularity in the subdivision – we just end up with a large # of different submodules Regularity as a guide subdivide into a set of similar building blocks – e.g. RAM composed of identical cells Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible
  21. 21. 21 Copyright 2001 © Mani Srivastava Regularity (contd.) Regularity can be at all levels circuit: use identically sized transistors gate: similar gate structures higher level: architectures with identical processors Regularity helps in many ways correct by construction reuse of design simplify verification of correctness
  22. 22. 22 Copyright 2001 © Mani Srivastava Circuit-level Regularity Example A 2-1 Mux D-type edge triggered flipflop One-bit full add All designed using inverter and tristate buffer
  23. 23. 23 Copyright 2001 © Mani Srivastava Modularity Condition that submodules have “well-defined” functions and interfaces in addition to regularity and hierarchy ‘Well-formed” modules allow their interaction with others to be “well-characterized” Depends on the situation e.g. in s/w a subroutine has a well-defined interface – argument list with typed variables e.g. in IC a well-defined physical, structural, and behavioral interface – pin position, layer, size, signal type, electrical characteristics, logic function
  24. 24. 24 Copyright 2001 © Mani Srivastava Why Modularity? Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined Allows team design by a number of designers Examples: bad use: use of transmission gates as inputs – internal signals now depend on source impedance bad use: use dynamic CMOS logic but fail to latch or register the inputs – timing of each module will have to be checked
  25. 25. 25 Copyright 2001 © Mani Srivastava Example of Poor Modularity
  26. 26. 26 Copyright 2001 © Mani Srivastava Locality Modularity provided “well-characterized” interfaces internals of modules unimportant to exterior interface • internal details remain at the local level a form of “information hiding” • reduces apparent complexity of the module Locality ensures that connections are between neighboring modules, avoiding long-distance connections Example: timing locality so that time critical operations are local • clock generation and distribution network • entire clock cycle for global signals to traverse chip • placement so that global wiring is minimized Analogy with software • global variables are to be avoided
  27. 27. 27 Copyright 2001 © Mani Srivastava Parallels between H/W & S/W Design Strong parallels in the way VLSIs are designed and the way complex software is HDLs used to describe hardware systems in essence merge these two disciplines software methods used to define hardware Hardware-software Co-design But, can’t ignore hardware aspects entirely important since a physical chip is the end product
  28. 28. 28 Copyright 2001 © Mani Srivastava Typical VLSI Design Flow
  29. 29. 29 Copyright 2001 © Mani Srivastava Types of Tools Analysis and verification Implementation and synthesis Testability techniques
  30. 30. 30 Copyright 2001 © Mani Srivastava Design Analysis and Verification Accounts for largest fraction of design time More efficient when done at higher levels of abstraction select of correct analysis level can reduce verification time by orders of magnitude Two approaches: simulation: depends on choice of excitation verification: extracts desired results directly from circuit description [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  31. 31. 31 Copyright 2001 © Mani Srivastava Simulation Approaches Key distinction is how are data & time represented? Circuit-level simulation (e.g. Spice) Switch-level simulation (e.g. IRSIM) – transistors as switches with resistance Gate-level (logic) simulation – now obsolete due to logic synthesis Functional simulation (e.g. VHDL, Verilog) – primitives of arbitrary complexity Behavioral simulation (e.g. VHDL) – only mimic I/O functionality – hardware delay loses its meaning
  32. 32. 32 Copyright 2001 © Mani Srivastava Digital Data as Analog Signals VD D Sp Vin Vou t 5.0 Bp 3.0 Vo ut (V) Gn ,p In Dn,p Out t pHL 1.0 Bn Sn –1.0 0 0.5 1 1.5 2 t (nsec) Circuit Simulation Both Time and Data treated as Analog Quantities Also complicated by presence of non-linear elements (relaxed in timing simulation). Impractical for large circuits [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  33. 33. 33 Copyright 2001 © Mani Srivastava Representing Data as Discrete Entity V 0 1 0 V DD VM R p t1 t2 t CL Discretizing the data using switching threshold R n {0,1,X} representation of data The linear switch model of the inverter [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  34. 34. 34 Copyright 2001 © Mani Srivastava Discretizing Time Evaluate circuits only at “interesting” times Event-driven simulation evaluate gates only at a future time of interest – current time + gate delay – for more accuracy gate delay = function of load still, events can happen at any time Further simplification: unit-delay model events only at multiples of a unit time Even further simplification: zero-delay model events at clock a.k.a. clock or cycle based simulation
  35. 35. 35 Copyright 2001 © Mani Srivastava Circuit vs. Switch Level Simulation 5.0 CIN OUT[2] 3.0Circuit OUT[3] 1.0 –1.0 0 5 10 15 20 time (nsec) Switch [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  36. 36. 36 Copyright 2001 © Mani Srivastava Structural Description of Accumulator entity accumulator is port ( -- definition of input and output terminals DI: in bit_vector(15 downto 0) -- a vector of 16 bit wide DO: inout bit_vector(15 downto 0); CLK: in bit ); end accumulator; architecture structure of accumulator is component reg -- definition of register ports port ( DI : in bit_vector(15 downto 0); Design defined as composition of DO : out bit_vector(15 downto 0); register and full-adder cells (“netlist”) CLK : in bit ); Data represented as {0,1,Z} end component; component add -- definition of adder ports port ( IN0 : in bit_vector(15 downto 0); IN1 : in bit_vector(15 downto 0); OUT0 : out bit_vector(15 downto 0) Time discretized and progresses with ); unit steps end component; -- definition of accumulator structure signal X : bit_vector(15 downto 0); begin add1 : add Description language: VHDL port map (DI, DO, X); -- defines port connectivity reg1 : reg Other options: schematics, Verilog port map (X, DO, CLK); end structure; [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  37. 37. 37 Copyright 2001 © Mani Srivastava Behavioral Description of Accumulator entity accumulator is port ( DI : in integer; DO : inout integer := 0; CLK : in bit ); end accumulator; Design described as set of input-output relations, regardless of chosen architecture behavior of accumulator is begin implementation process(CLK) variable X : integer := 0; -- intermediate variable begin if CLK = 1 then Data described at higher abstraction X < = DO + D1; DO <= X; level (“integer”) end if; end process; end behavior; [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  38. 38. 38 Copyright 2001 © Mani Srivastava Behavioral Simulation of Accumulator Discrete time Integer data (Synopsys Waves display tool) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  39. 39. 39 Copyright 2001 © Mani Srivastava Timing Verification Critical path Enumerates and rank orders critical timing paths No simulation needed! (Synopsys-Epic Pathmill) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  40. 40. 40 Copyright 2001 © Mani Srivastava Issues in Timing Verification In 4 - b it a d d e r O ut M U X bypass False Timing Paths [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  41. 41. 41 Copyright 2001 © Mani Srivastava Design Verification Simulation only tells how circuit reacted to input excitation that was specified Verification tools analyze design and find problems Example: electrical verification – transistor sizing for rise/fall time constraints timing verification – find critical path functional (formal) verification – compare circuit behavior against designer’s specification – proof that the two are “equivalent”, i.e. proof that the circuit will work – e.g. prove that two state machines are equivalent
  42. 42. 42 Copyright 2001 © Mani Srivastava Implementation Methodologies Digital Circuit Implementation Approaches Custom Semi-custom Cell-Based Array-Based Standard Cells Macro Cells Pre-diffused Pre-wired Compiled Cells (Gate Arrays) (FPGA) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  43. 43. 43 Copyright 2001 © Mani Srivastava Economics of Implementation Decision depends on Non-recurring engineering cost – engineering design cost (personnel, support etc.) – prototype manufacturing cost Production cost (Recurring cost) – wafer cost, processing cost – die per wafer – die yield per wafer, packaging yield, final test yield Fixed costs – data sheets, cost of sales Important to estimate design time and design cost guide to select the design method
  44. 44. 44 Copyright 2001 © Mani Srivastava Choosing a Design Style Custom Cell-based Prediffused Prewired Density Very High High High Medium-Low Performance Very High High High Medium-Low Flexibility Very High High Medium Low Design Time Very long Short Short Very Short Manufacturing Time Medium Medium Short Very Short Cost – low volume Very High High High Low Cost – high volume Low Low Low High
  45. 45. 45 Copyright 2001 © Mani Srivastava Custom Circuit Design When performance & design density important High cost and long time-to-market justified only if – high volumes – design will be reused (e.g. library cell) – cost no concern due to CAD tools, custom design is minimal
  46. 46. 46 Copyright 2001 © Mani Srivastava Tools for Custom Design Layout editor (e.g. Virtuoso) Symbolic layout relative positioning followed by compactor Design rule checking technology file, hierarchical DRC Circuit extraction schematic from layout transistors, caps, resistances, inductances Netlist comparison and netlist isomorphism Back annotation from layout to schematic
  47. 47. 47 Copyright 2001 © Mani Srivastava Custom Design - Layout Editor Magic Layout Editor (UC Berkeley) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  48. 48. 48 Copyright 2001 © Mani Srivastava Symbolic Layout V D D 3 In O ut • Dimensionless layout entities • Only topology is important 1 • Final layout generated by “compaction” program G N D Stick diagram of inverter [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  49. 49. 49 Copyright 2001 © Mani Srivastava Cell-based Design Methodology Why? Shorter design time! but, larger penalty Array-based design (later) cuts process steps and reduces time even further… Standard cell library of logic gate (nand, and, or etc.) design as a schematic or netlist of cells from library layout is generated automatically in rows design and composition of library is the main issue – what fanout to design for?
  50. 50. 50 Copyright 2001 © Mani Srivastava Standard Cell Libraries Typically contain a few hundred cells inverters, NAND gates, NOR gates, complex AOI, OAI gates, D- latches, and flip-flops Each gate type can have multiple implementations to provide adequate driving capability for different fanouts e.g the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors the chip designer can choose the proper size to achieve high circuit speed and layout density Cells characterized for various metrics, such as delay time vs. load capacitance Circuit, timing, and fault simulation models cell data for place-and-route mask data Cells designed such that they can be abutted to form rows
  51. 51. 51 Copyright 2001 © Mani Srivastava Standard Cell Based Design Logic Cell Feedthrough Cell Routing Channel Rows of Cells Routing channel requirements are reduced by presence Functional of more interconnect Module layers (RAM, multiplier, …) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  52. 52. 52 Copyright 2001 © Mani Srivastava Standard Cell - Example [Brodersen92] [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  53. 53. 53 Copyright 2001 © Mani Srivastava Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  54. 54. 54 Copyright 2001 © Mani Srivastava Automatic Cell Generation (Compiled Cells) Random-logic layout generated by CLEO cell compiler (Digital) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  55. 55. 55 Copyright 2001 © Mani Srivastava Module Generators Logic gate okay for random logic But, inefficient for regular structures e.g. carry chain capacitance in N-bit adder Standard cells do not exploit regularity Structured custom design macrocell generators, e.g. memories, multipliers – interconnects by abutment in both dimensions datapath compilers – abutment in one dimension, routing in the other usually “parameterizable”
  56. 56. 56 Copyright 2001 © Mani Srivastava Datapath Compilers: Linear Placement bus0 buffer adder bus2 mux reg0 bus1 reg1 routing area feed-through bit-slice Advantages: One-dimensional placement/routing problem [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  57. 57. 57 Copyright 2001 © Mani Srivastava Datapath Layout
  58. 58. 58 Copyright 2001 © Mani Srivastava Macrocell Design Methodology MacrocellFloorplan: Interconnect BusDefines overalltopology of design,relative placement ofmodules, and globalroutes of busses, Routing Channelsupplies, and clocks [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  59. 59. 59 Copyright 2001 © Mani Srivastava Channel Routing
  60. 60. 60 Copyright 2001 © Mani Srivastava Macrocell-based Design Example SRAM SRAM Routing Channel Data paths Standard cells Video-encoder chip [Brodersen92] [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  61. 61. 61 Copyright 2001 © Mani Srivastava Array-based Design Cuts process steps and reduces time even further… Several types: Mask programmable arrays – pre-diffused so that several masks are eliminated – typically, only top metalization needs to be done – standard packages to keep packaging cost low – e.g. gate array, sea of gates Pre-wired arrays – avoid detailed manufacturing totally – analogy with memory
  62. 62. 62 Copyright 2001 © Mani Srivastava Processing Steps in Gate Array Implementations
  63. 63. 63 Copyright 2001 © Mani Srivastava Gate Array - Sea-of-gates polysilicon VD D metal rows of Uncommited uncommitted possible cells GND contact Cell In 1 In2 In3 In4 routing channel Committed Cell (4-input NOR) Out [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  64. 64. 64 Copyright 2001 © Mani Srivastava Sea-of-gate Primitive Cells O x id e - i s o l a t io n PM O S PMOS NM OS NM OS NM OS Using oxide-isolation Using gate-isolation [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  65. 65. 65 Copyright 2001 © Mani Srivastava Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 µm CMOS) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  66. 66. 66 Copyright 2001 © Mani Srivastava Pre-wired Arrays Categories of pre-wired arrays (or, field programmable gate arrays) fuse based (program once) non-volatile EPROM or EEROM based RAM based [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  67. 67. 67 Copyright 2001 © Mani Srivastava Programmable Logic Devices PLA PROM PAL [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  68. 68. 68 Copyright 2001 © Mani Srivastava EPLD Block Diagram Primary inputs Macrocell Courtesy Altera Corp. [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  69. 69. 69 Copyright 2001 © Mani Srivastava Antifuse Normally high resistance (> 100 MΩ) on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200-500Ω)
  70. 70. 70 Copyright 2001 © Mani Srivastava Antifuse-based Actel FPGAs I/O B u ffe r s P r o g r a m / T e s t / D ia g n o s t i c s V e r ti c a l ro u te s Standard-cell like floorplan I/O B u ffe r s I/O B u ffe rs R o w s o f lo g i c m o d u le s R o u tin g c h a n n e ls I/O B u ffe r s [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  71. 71. 71 Copyright 2001 © Mani Srivastava Detailed Interconnect P r o g r a m m e d in t e r c o n n e c t io n I n p u t/o u tp u t p in C e ll A n tifu s e H o r iz o n ta l tr a c k s V e r t ic a l t r a c k s Programming interconnect using anti-fuses [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  72. 72. 72 Copyright 2001 © Mani Srivastava Basic Block in Actel FPGA
  73. 73. 73 Copyright 2001 © Mani Srivastava RAM-based FPGAs CLB CLB switching matrix Horizontal routing channel Interconnect point CLB CLB Vertical routing channel [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  74. 74. 74 Copyright 2001 © Mani Srivastava Basic Block (CLB) in RAM-based FPGAs C o m b in a tio n a l lo g ic S to ra g e e l e m e n ts R A D in R Any function of up to B /Q 1 /Q 2 4 variables F D Q 1 F C /Q 1 /Q 2 G CE F D A Any function of up to B /Q 1 /Q 2 4 variables R G F D Q 2 C /Q 1 /Q 2 G D G CE E C lo c k C E Courtesy of Xilinx [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  75. 75. 75 Copyright 2001 © Mani Srivastava RAM-based FPGA Xilinx XC4025 [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  76. 76. 76 Copyright 2001 © Mani Srivastava General Architecture of Xilinx FPGAs
  77. 77. 77 Copyright 2001 © Mani Srivastava Switch Matrices & Interconnection between CLBs
  78. 78. 78 Copyright 2001 © Mani Srivastava XC2000 CLB of the Xilinx FPGA
  79. 79. 79 Copyright 2001 © Mani Srivastava Overview of VLSI Design Styles
  80. 80. 80 Copyright 2001 © Mani Srivastava Design synthesis Behavior → Structure
  81. 81. 81 Copyright 2001 © Mani Srivastava Taxonomy of Synthesis Tasks A rc h it e c t u r a l L e v e l L o g ic L e ve l C irc u it L e v e l s t a te a B e h a v i o ra l V ie w ( i: 1 ..1 6 ) :: 0 b sum = su m *z–1 + 2 1 c o e ff[i]* In * z – 1 c x 3 tp A r c h i t e c tu r e L o g ic C irc u it S y n t h e s is S y n t h e s is S y n t h e s is S t r u c t u r a l V ie w a 4 mem b fs m x c a 2 * 1 c b 2 D [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
  82. 82. 82 Copyright 2001 © Mani Srivastava Circuit Synthesis Logic equations → transistor schematics selection of circuit style – complementary static, pass-transistor, dynamic etc. construction of logic network – e.g. Euler path techniques Transistor sizing to meet performance constraints – major impact on area, power, timing subtle process… sensitive to parasitics – usually circuit modeled by equivalent RC circuit – detailed knowledge of subsequent layout process needed for estimation of parasitic capacitances
  83. 83. 83 Copyright 2001 © Mani Srivastava RTL or Logic Synthesis Generate structural view of a logic level network Many ways of specifying: FSMs, schematics, boolean equations, HDL etc. Two step process: technology independent phase – logic optimized using boolean & algebraic manipulation technology mapping phase
  84. 84. 84 Copyright 2001 © Mani Srivastava Evolution of RTL Synthesis 2-Level logic minimization Espresso from Berkeley Suited for PLAs & PALs which were used a lot in 80s Sequential and state-machine synthesis state minimization, state encoding Multilevel logic synthesis Mis-II from Berkeley standard-cell and FPGA Full blown RTL synthesis from HDL e.g. Synopsys’s VHDL compiler, Berkeley’s SIS
  85. 85. 85 Copyright 2001 © Mani Srivastava Example: Multi-level Logic Synthesis Adder: S = (A ⊕ B) ⊕ Ci Co = A.B + A.Ci + B.Ci
  86. 86. 86 Copyright 2001 © Mani Srivastava Architecture Synthesis Also called behavior or high-level synthesis Generate architecture from task description under constraints on area, speed, power etc. Three phases allocation: figures out busses, execution units etc. assignment: binds behavior operations to hardware resources scheduling: order of operations Also, transformations that manipulate input behavior to obtain superior solution pipelining, parallelization etc.
  87. 87. 87 Copyright 2001 © Mani Srivastava Example of Architecture Synthesis ;
  88. 88. 88 Copyright 2001 © Mani Srivastava Alternative Solution
  89. 89. 89 Copyright 2001 © Mani Srivastava Design-Evaluation Space
  90. 90. 90 Copyright 2001 © Mani Srivastava Design-Evaluation Space for a Logic Function
  91. 91. 91 Copyright 2001 © Mani Srivastava Area, Latency, Cycle-time Design Evaluation Space
  92. 92. 92 Copyright 2001 © Mani Srivastava Another Example of Architecture Synthesis
  93. 93. 93 Copyright 2001 © Mani Srivastava Alternative Implementations

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