Memoria Interna
Ing. Andrés Larco

www.virtualepn.edu.ec
andres.larco@epn.edu.ec
0984510099
Semiconductor Memory
• RAM
—Misnamed as all semiconductor memory is
random access
—Read/Write
—Volatile
—Temporary storage...
Memory Cell Operation
Dynamic RAM Structure
Types of ROM
• Written during manufacture
—Very expensive for small runs

• Programmable (once)
—PROM
—Needs special equip...
Interleaved Memory
• Collection of DRAM chips
• Grouped into memory bank
• Banks independently service read or write
reque...
SDRAM
DDR SDRAM
• SDRAM can only send data once per clock
• Double-data-rate SDRAM can send data
twice per clock cycle
—Rising e...
DDR SDRAM
Read Timing
Simplified DRAM Read Timing
Cache DRAM
• Mitsubishi
• Integrates small SRAM cache (16 kb) onto
generic DRAM chip
• Used as true cache
—64-bit lines
—E...
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Memoria interna

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Memoria interna

  1. 1. Memoria Interna Ing. Andrés Larco www.virtualepn.edu.ec andres.larco@epn.edu.ec 0984510099
  2. 2. Semiconductor Memory • RAM —Misnamed as all semiconductor memory is random access —Read/Write —Volatile —Temporary storage —Static or dynamic
  3. 3. Memory Cell Operation
  4. 4. Dynamic RAM Structure
  5. 5. Types of ROM • Written during manufacture —Very expensive for small runs • Programmable (once) —PROM —Needs special equipment to program • Read “mostly” —Erasable Programmable (EPROM) – Erased by UV —Electrically Erasable (EEPROM) – Takes much longer to write than read —Flash memory – Erase whole memory electrically
  6. 6. Interleaved Memory • Collection of DRAM chips • Grouped into memory bank • Banks independently service read or write requests • K banks can service k requests simultaneously
  7. 7. SDRAM
  8. 8. DDR SDRAM • SDRAM can only send data once per clock • Double-data-rate SDRAM can send data twice per clock cycle —Rising edge and falling edge
  9. 9. DDR SDRAM Read Timing
  10. 10. Simplified DRAM Read Timing
  11. 11. Cache DRAM • Mitsubishi • Integrates small SRAM cache (16 kb) onto generic DRAM chip • Used as true cache —64-bit lines —Effective for ordinary random access • To support serial access of block of data —E.g. refresh bit-mapped screen – CDRAM can prefetch data from DRAM into SRAM buffer – Subsequent accesses solely to SRAM

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