Del oral question

1,270 views

Published on

Published in: Technology, Business
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
1,270
On SlideShare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
Downloads
21
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Del oral question

  1. 1. Digital Electronics Laboratory 1. Differentiate between analog and digital signals. 2. What is the principle cause of propagation delay time in P-N junction diode? 3. What is the meaning of LS in 74LS76? 4. Why n-p-n transistors are preferred over p-n-p transistors in digital ckt. 5. Why C.E. configuration is commonly employed for transistor as switch? 6. Define the “turn on” and “turn off” timings of BJT. 7. Define the terms “Rise Time” and “fall time”. 8. Define “propagation time delay” of logic gate 9. Define the term “fig. of merit” of a logic gate. 10. Define the terms “fan out” and “fan in”. 11. Define” noise margin” 12. Which is the fastest Logic family. 13. Define the following: bit, nibble, byte, word, literal, STD SOP, STD POS. 14. What is meant by natural BCD code & excess-3 code? 15. Why hexadecimal code widely used in digital systems? 16. What is MUX, DEMUX, decoder, encoder? 17. Compare: 1. Mux & encoder 2. Demux & decoder 3. Encoder & decoder 18. Why are subtractor ICs not available? 19. What is the significance of bubble in logic ckt? 20. What is filp-flop? 21. Explain the functions of asynchronous i/ps in flip flops. 22. What is meant by race & race around condition in flip-flops? 23. Design T-type by using D-type flip flop & vice versa. 24. Differentiate between truth table & excitation table. 25. Differentiate between latch & flip flop. 26. How can you prevent race and race around condition in flip-flop? 27. What are different methods used for triggering flip-flops. 28. Explain level triggered, negative edge triggered flip-flop. 29. Differentiate between combinational logic ckt. And sequential logic ckt. 30. Differentiate between synchronous and asynchronous counter. 31. What is meant by delay line, modulus of a counter? Prof P P Ghadekar, VIT Pune  
  2. 2. 32. What is meant by “bush” diag. and lock out condition? How can we prevent lock outcondition? 33. What is meant by “state table” and “state diag.?” 34. What is meant by reduction in the design of sequential ckt? 35. Define clock. Why do we use it? 36. Differentiate between ripple counter and twisted counter. 37. Define end around carry. 38. What is meant by FIFO and LIFO? 39. Differentiate between Full-adder and Half-adder. 40. What is meant by glitch? 41. Why propagation delay occurs in digital circuit or gate? 42. Explain application of the following codes i. Binary ii. Gray iii. Excess-3 iv. BCD v. Hex 43. State De’Morgan’s Theorem 44. What do you understand by universal logic gate? 45. Differentiate between active and passive pull-up. 46. What is meant by an active low i/p, active low o/p? 47. What is meant by a. Bipolar logic family. b. Unipolar logic family. 48. Differentiate between saturated and non-saturated logic. 49. Define the terms SSI, MSI, LSI & VLSI. Also define voltage parameters of Digital ICs, as well as their current parameters. 50. Differentiate between DC & AC noise margins. 51. What is meant by ‘Wired Logic’? 52. Explain Tri-state logic (TSL). 53. What are the advantages of the CMOS logic? 54. Why LSI & VLSI devices are not available in TTL? 55. What is meant by LSD & MSD? 56. Explain sign-magnitude representation of numbers. 57. What is meant by parity of digital word? 58. What is AND-OR realization, OR-AND realization, NAND-NAND realization, NOR- NOR realization? 59. What is a code converter? 60. What is the type of display device used in your calculator? 61. What is meant by ‘Temporal code’ & ‘Special code’? 62. Define the following terms i. Pulse width. Prof P P Ghadekar, VIT Pune  
  3. 3. ii. Pulse repetition. iii. Duty cycle. 63. How is memory size specified? 64. What does RAM ROM stand for? 65. What are the different types of read-only memories? 66. Why Fan-out is very high for MOS devices? 67. Differentiate between EPROM and E2PROM? 68. What are the advantages of dynamic RAM over static RAM? 69. What is the difference between PLA and ROM? 70. What are self-complementing codes? 71. Differentiate between K-Map and Quine-McCluskey method. 72. Differentiate between Synchronous and Asynchronous sequential circuits. 73. Differentiate – i. Moore and Mealy models. ii. ASM & RTL. iii. RTL & Flow chart. 74. Differentiate: i. 7490 & 74190 ii. 74191 & 7493 75. What are the disadvantages of parity bits? 76. What are the practical applications of parity bits? 77. What are the applications of Ripple counter & Synchronous counter? 78. What is meant by Pseudo-Random Sequence generator? 79. Differentiate between Shift register and Barrel Shifter. 80. Explain basic components of ASM. 81. Explain Transfer statement and Branch statement of RTL. 82. How can we realize sequential circuit described by ASM chart? 83. Differentiate between multiplexer control method & K-map simplification method. 84. What are the applications of Waveform generator? 85. Write RTL notations for left shift, right shift, left rotate, right rotate operation. 86. Write RTL notations to perform logical operations. 87. What is meant by CSL & CSP signal in RTL? 88. How can we perform BCD subtraction by using 9’s complement method & by using 10’s complement method? 89. How can we improve speed f operation of addition process?(Carry look-ahead generator) 90. Draw Truth-table for Full-adder, Full-subtractor. 91. How can we prepare Truth-table & excitation table of FFs. 92. Design Full adder, Full subtractor, Mux, Decoder, JK Flip-Flop, D-type FF, T-type FF by using logic gates. 93. Design full adder, full subtractor, comparator, parity generator, parity checker, by using Mux & Decoder. 94. Design 8-bit BCD adder. 95. Design Full adder, Full subtractor by using NAND gate & by using NOR gate only. 96. What are the application of D-type FF & T-type FF? 97. Draw Master-Slave FF & explain its working. 98. What is meant by SISO, SIPO, PIPO, PISO? Prof P P Ghadekar, VIT Pune  
  4. 4. 99. What are the applications of Pseudo Random Sequence generator? 100. Design 4-bit Pseudo-Random Sequence generator by using left shift and right shift register. 101. Design bi-directional & unidirectional shift register by using JK FF & some logic gates. 102. What is the range of temperature in which 74-series of TTL ICs can be used? 103. Why MOS logic is mainly used for LSI & VLSI applications? 104. Compare speed of operation of bipolar & MOS logic. 105. Explain the meaning of following symbols used in 54/74 series TTL ICs : L, H, LS, S, AS, ALS. 106. Which of the 74 series TTL ICs has the best figure of merit & what is its value? -ALS. its figure of merit is 4 PJ. 107. Which type of TTL gates can drive CMOS gates? -TTL with open collector output can drive0 CMOS. 108. Which is the fastest series in54/74 TTL logic family?-advanced schottky (AS) is the fastest series. it has gate propagation delay time of 1.5 ns & maxclk freq of the f/f 175Mhz 109. Why NAND-NAND realization is preferred over AND-OR realization?-this read only one kind of gates (NAND) which minimizes IC package count. 110. Why decimal 6 is reqd to be added in BCD adder if the sum is not valid BCD no.?-16 possible combinations are there with 4-bit numbers. In BCD only ten of these are used andeither six are skipped. That is why 6 is reqd to be added.111. How do you give inputs to your calculator i.e. how do you feed information, such asnumbers to be manipulated, operations to be performed etc.-the inputs are given through switches. When a switch is pressed it generates a binary codecorresponding to that switch.112. Explain different cascading methods of IC 74190?-binary counter 74190Fout=fin/N, 1<=N<=15(for down counting)Fout= fin/(15-N), 0<=N<=14(for up counting) Decade counter 74190 Prof P P Ghadekar, VIT Pune  
  5. 5. Fout=fin/N for 1<=N<=9(for down counting)Fout= fin/(9-N) for 1<=N<=8(for up counting)114. Calculate propagation delay of synchronous counter, if propagation delay of FF is 100ms &gate is 50ms.- PD= (td) ff+ (td) gate115. Calculate propagation delay of asynchronous counter if PD of FF is 100ms. no. of FFs are5.-PD= n*(td)116. Explain steps to convert binary to gray and gray to binary?117. How does error detection takes place using parity bits. When does parity chking fail todetect errors?118. Comparison of TTL, CMOS& ECL.-Parameters TTL CMOS ECLPropagation delay 10ns 70ns 500psNoise margin 0.4V 0.45V 150mVPower dissipation 10mW 0.01mW 5mWFan out 10 50 25Figure of merit 100pj 0.7pj 0.5pj119 comparison of synchronous& asynchronous sequential ckt.Synchronous AsynchrousThese ckts are easy to design Difficult to designA clocked FF acts as a memory element An unclocked FF or time delay element is used as memory elementsSlower, because the delays correspond to those Faster as the clk is not present.of the memory element.Status of memory element is affected only at The status of memory element will change anythe active edge of clk of the input is changed time as the i/p is changed120. How does computer store sign data in memory?- Computer uses 2.5compliment tech to store sign data in memory. Prof P P Ghadekar, VIT Pune  
  6. 6. 121. Design bounce-elimination switch by s-r ff.122. Design T ff using S R ff123. Define noise immunity, noise margin. How can we calculate 1 state noise margin and 0state noise margin?124. What happens if output accidentally get shorted to ground in?1) NMOS 2) CMOS125. IS it possible to drive CMOS using TTL? How?126. Is it possible to drive TTL using CMOS? How?127. Why gray codes are used to decode shaft encoder128. IC no of 4-bit comparator, ALU, parity checker.129. Application of ring counter and twisted ring counter.130. Design sequence generator for given sequence using shift register.131. Differentiate between 54xx and 74xx series ICs132. Design hex keypad reader ckt by using counter, latch, decoder to decode key press.133. VHDL is acronym for134. Why need of VHDL generated in us135. Write down syntax for entity declaration, architecture body.136. Which architecture modeling is preferred?137. What are disadvantages of data flow architecture modeling style138. Write VHDL code for d ff with asynchronous input in all modeling style.139. Why process statement we required can we process statement in concurrent statement.140. Different type of process-combinational process, cloced process141. What are different feature of VHDL142. Differentiate between PROM, PLA, PAL143. Explain in short the difference between CPLD & FPGA Prof P P Ghadekar, VIT Pune  
  7. 7. 144. What are FPGA?145. What are CPLD?146. What do you mean by ASIC?147. Give classification of PLD’s?148. What is programming logic array? How is it differs from ROM?149. What is PAL?150. What is IDE?-Integrated development environment- Prof P P Ghadekar, VIT Pune  

×