Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.
Graduate Student
University of Southern California
B.E. in Electronics and Communication
Visvesvaraya Technological University
Dharwad, KA, India
Graduation: June 2013
Secur...
Designed and implemented a 32 Bit Out of Order execution and In-order
completion Tomasulo Processor on Artix 7 FPGA board ...
Designed a 5-stage pipelined processor with custom ISA suitable for network
packet processing on NetFPGA. Integrated the p...
 Designed a circuit preprocessor, ATPG (PODEM and D-algorithm)
and Deductive Fault Simulator for combinational circuits u...
 Design of 5 stage pipelined processor with hardware and software
components
 Design and layout of a full custom general...
 Automated Verilog code generation for Parallel Cyclic Redundancy
Check - Perl Scripting
 Managed to calculate CRC in a ...
Co-Op Engineer
Advanced Micro Devices (AMD)
Sunnyvale, CA, USA
Associate Software Engineer
Accenture Services
Bangalore, I...
 Working in the CORES LS team that deals with design verification
of microarchitecture for CPU cores.
 Current Responsib...
Akshay_Desai_ppt
Akshay_Desai_ppt
Akshay_Desai_ppt
Akshay_Desai_ppt
Upcoming SlideShare
Loading in …5
×

Akshay_Desai_ppt

297 views

Published on

  • Be the first to comment

  • Be the first to like this

Akshay_Desai_ppt

  1. 1. Graduate Student University of Southern California
  2. 2. B.E. in Electronics and Communication Visvesvaraya Technological University Dharwad, KA, India Graduation: June 2013 Secured 5th Rank in the department. M.S. in Electrical Engineering University of Southern California Los Angeles, CA, USA Coursework: Digital VLSI and Computer Architecture Expected Graduation: May 2016
  3. 3. Designed and implemented a 32 Bit Out of Order execution and In-order completion Tomasulo Processor on Artix 7 FPGA board in VHDL.  Features  2 bit Branch Prediction Buffer to improve the reliability of Branch Prediction.  Two Stage Dispatch Unit for dispatching new instructions.  Copy Free Check-pointing(CFC) , Free Register List(FRL) and Register Alias Table(RAT) for efficient handling of Speculative execution.  Issue Unit for handling Issuing of Instructions from the four Issue Queues based on their variable latency.  32 location Reorder Buffer (ROB) for handling In Order Completion of Requests.  Store Address Buffer for Memory Disambiguation.  Store Buffer and Load/Store Buffer for handling variable cache latency of Load and Store words
  4. 4. Designed a 5-stage pipelined processor with custom ISA suitable for network packet processing on NetFPGA. Integrated the processor in reference router architecture and emulated the design in DeterLab testbed.  Features  Custom ISA - Designed a C compiler using Perl scripting language to facilitate the conversion of a C-code to custom ISA.  ILP - Fine grained dual thread processing support.  Hardware accelerator - For deep packet inspection using schematics, IP Cores, and Verilog. Achieved 20+ patterns detection at 1Gbps line speed.  Inter-convertible FIFO-SRAM.  Project Website : http://teamjarvis.weebly.com/
  5. 5.  Designed a circuit preprocessor, ATPG (PODEM and D-algorithm) and Deductive Fault Simulator for combinational circuits using C language.  Deductive Fault Simulator  Simulates all the test vectors generated by ATPG.  Each node in the circuit has an associated list, implemented as a linked list.  The lists are operated on for performing fault propagation.  Calculated the fault coverage by comparing the original fault list and all the propagated faults.  3 ISCAS circuits were used as a benchmark  Achieved 100% fault coverage on two circuits and 97% on the third.
  6. 6.  Design of 5 stage pipelined processor with hardware and software components  Design and layout of a full custom general purpose 16-bit CPU with decoding logic, register files, ALU, memory unit(512 bit SRAM) and other circuitry that supports 14 different instructions in Cadence Virtuoso.  Implemented instruction fetching, decoding, dependency handling and automated back end result verification using Perl.  Design of DDR3 memory controller – Complete ASIC flow  Designed Initialization engine and Processing logic of the memory controller for Micron DDR3 SRAM to support scalar, burst and atomic read/write operations using Verilog.  Synthesized the RTL design to gate level using Synopsys DC, performed STA using Synopsys PrimeTime.  Performed Logical Equivalency Checking using Cadence Conformal, APR and CTS using Cadence SOC Encounter.
  7. 7.  Automated Verilog code generation for Parallel Cyclic Redundancy Check - Perl Scripting  Managed to calculate CRC in a single clock suitable for error checking in DDR DIMMs with ECC bits used in memory controllers  Used Perl to generate Verilog module for parameterized parallel CRC with the user-defined arbitrary data width and polynomial function.  Automatic layout router - Verilog RTL Design  Implemented Lee’s algorithm for routing the shortest path from source to target on a 8x8 grid using Manhattan style connection in Verilog.  Improved the efficiency of Lee’s algorithm by two ended search wave propagation and reduced the execution time by 40%.
  8. 8. Co-Op Engineer Advanced Micro Devices (AMD) Sunnyvale, CA, USA Associate Software Engineer Accenture Services Bangalore, India Graduate Student Researcher Advisor: Dr. Alice Parker USC
  9. 9.  Working in the CORES LS team that deals with design verification of microarchitecture for CPU cores.  Current Responsibilities  Involved in unit level functional verification of load store architecture and test infrastructure development for verifying architectural features.  Designing directed testcases in C++ to debug and verify cache preloading, paging related issues and debug related to memory access types. Using Synopsys Verdi for RTL analysis.  Debugging memory leaks using memcheck tool of Valgrind framework.  Future Tasks  I will be working on development of Coverage infrastructure, verifying multithread compatibility of new features and stimulus cleanup.

×