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Wishbone interface and bus cycles

WISHBONE interface specification and classic bus cycles

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Wishbone interface and bus cycles

  1. 1. Hanbat Hanbat National National University University Wishbone InterfaceWishbone Interface SpecificationSpecification andand Classic Bus CycleClassic Bus Cycle NameName SoC Design Lab.SoC Design Lab. June.19.2014
  2. 2. ContentsContents  Interface Specification  Classic Bus Cycle 2
  3. 3. Wishbone DatasheetWishbone Datasheet  Wishbone specification requires that interfaces must be documented through a wishbone datasheet  The standard does not specify the form of the datasheet  The datasheet could be part of a comment field in an HDL source file or part of the reference manual for the IP core  The datasheet helps end users understand the operation of the core and how to connect it to other cores 3
  4. 4. Wishbone DatasheetWishbone Datasheet  8-bit wishbone slave output port 4 Description Specification General description: 8-bit slave output port Supported cycles: SLAVE, READ/WRITE SLAVE, BLOCK READ/WRITE SLAVE, RMW Data port, size: Data port, granularity: Data port: max operand size: Data transfer ordering: Data transfer sequencing: 8-bit 8-bit 8-bit Big endian and/or little endian Undefined Supported signal list and cross reference to equivalent WISHBONE signals Signal name wishbone equiv. ACK_O ACK_O CLK_I CLK_I DAT_I(7..0) DAT_I() DAT_O(7..0) DAT_O() RST_I RST_I STB_I STB_I WE_I WE_I RESET CE D Q DAT_O(7..0) DAT_I(7..0) CLK_I RST_I ACK_O STB_I WE_I
  5. 5. Signal NamingSignal Naming  Signal names must adhere to the rules of the tool in which the IP core was designed  Any signal name may be used to describe wishbone signals but it is recommended to use the standard names 5
  6. 6. Logic LevelsLogic Levels  All wishbone interface signals must use active high logic  Generally, active low signals does not present a problem  However, some tools do not have a standard way of indicating an active low signal  Using [#RST_I], [/RST_I] or [N_RST_I] to represent active low reset may cause confusion among users and incompatibility between modules 6
  7. 7. Wishbone Signal DescriptionWishbone Signal Description  SYSCON module signals 7 Signal name description CLK_O It coordinates all activities for the internal logic within the WISHBONE interconnect. The INTERCON module connects the [CLK_O] output to the [CLK_I] input on MASTER and SLAVE interfaces. RST_O It forces all WISHBONE interfaces to restart. All internal self-starting state machines are forced into an initial state. The INTERCON connects the [RST_O] output to the [RST_I] input on MASTER and SLAVE interfaces RST_I CLK_I CLK_I DAT_IO DAT_IO WE_O WE_I STB_O STB_O ACK_I ACK_O CYC_O CYC_I TG_IO TG_IO SYSCON WISHBONEMASTER WISHBONESLAVE CLK_ORST_O
  8. 8. Wishbone Signal DescriptionWishbone Signal Description  Signals common to MASTER and SLAVE interfaces 8 Signal name Description CLK_I All WISHBONE output signals are registered at the rising edge of [CLK_I]. All WISHBONE input signals are stable before the rising edge of [CLK_I]. DAT_I() The data input array [DAT_I()] is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. [DAT_I(63..0)]). DAT_O() The data output array [DAT_O()] is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. [DAT_I(63..0)]). RST_I() The reset input [RST_I] forces the WISHBONE interface to restart TGD_I() Data tag type [TGD_I()] is used on MASTER and SLAVE interfaces. It contains information that is associated with the data input array [DAT_I()], and is qualified by signal [STB_I]. TGD_O( ) Data tag type [TGD_O()] is used on MASTER and SLAVE interfaces. It contains information that is associated with the data output array [DAT_O()], and is qualified by signal [STB_O] 88 RST_I CLK_I CLK_I DAT_IO DAT_IO WE_O WE_I STB_O STB_O ACK_I ACK_O CYC_O CYC_I TG_IO TG_IO SYSCON WISHBONEMASTER WISHBONESLAVE
  9. 9. Wishbone Signal DescriptionWishbone Signal Description  MASTER signals 9 Signal name Description ACK_I The acknowledge input [ACK_I], when asserted, indicates the normal termination of a bus cycle CYC_O The cycle output [CYC_O], when asserted, indicates that a valid bus cycle is in progress STALL_I The pipeline stall input [STALL_I] indicates that current slave is not able to accept the transfer in the transaction queue ERR_I The error input [ERR_I] indicates an abnormal cycle termination RTY_I The retry input [RTY_I] indicates that the interface is not ready to accept or send data, and that the cycle should be retried STB_O The strobe output [STB_O] indicates a valid data transfer cycle WE_O The write enable output [WE_O] indicates whether the current local bus cycle is a READ or WRITE cycle RST_I CLK_I CLK_I DAT_IO DAT_IO WE_O WE_I STB_O STB_O ACK_I ACK_O CYC_O CYC_I TG_IO TG_IO SYSCON WISHBONEMASTER WISHBONESLAVE
  10. 10. Wishbone Signal DescriptionWishbone Signal Description  SLAVE signals 10 Signal name Description ACK_O The acknowledge output [ACK_O], when asserted, indicates the termination of a normal bus cycle CYC_I The cycle input [CYC_I], when asserted, indicates that a valid bus cycle is in progress STALL_O The pipeline stall signal [STALL_O] indicates that the slave can not accept additional transactions in its queue ERR_O The error output [ERR_O] indicates an abnormal cycle termination RTY_O The retry output [RTY_O] indicates that the indicates that the interface is not ready to accept or send data, and that the cycle should be retried STB_I The strobe input [STB_I], when asserted, indicates that the SLAVE is selected. A SLAVE shall respond to other WISHBONE signals only when this [STB_I] is asserted WE_I The write enable input [WE_I] indicates whether the current local bus cycle is a READ or WRITE cycle RST_I CLK_I CLK_I DAT_IO DAT_IO WE_O WE_I STB_O STB_O ACK_I ACK_O CYC_O CYC_I TG_IO TG_IO SYSCON WISHBONEMASTER WISHBONESLAVE
  11. 11. Wishbone Classic Bus CyclesWishbone Classic Bus Cycles  Wishbone classic bus cycles are described in term of:  Reset operation  Handshaking protocol  Data organization during transfers 11
  12. 12. Reset operationReset operation  [RST_O] is used to initialize all hardware interfaces to a pre-defined state  It can be asserted anytime and it is used for test simulation purposes 12
  13. 13. Transfer Cycle InitializationTransfer Cycle Initialization  MASTER interfaces initiate a transfer cycle by asserting [CYC_O]  SLAVE interfaces respond to other slave signals only when [CYC_I] is asserted 13
  14. 14. Handshaking protocolHandshaking protocol  All bus cycles use handshaking protocol between the master and slave interfaces  There exist two different traffic modes:  Standard  Pipelined 14
  15. 15. Standard wishbone protocolStandard wishbone protocol  MASTER asserts [STB_O] when it is ready to transfer data  [STB_O] remains asserted until the SLAVE asserts one of the cycle terminating signals: [ACK_I], [ERR_I] or [RTY_I]  Standard bus handshaking protocol with asynchronous slave: 15 CLK_I CYC_O STB_O ACK_I
  16. 16. Standard wishbone protocolStandard wishbone protocol  Master waits for ACK from slave before sending next instruction 16 MASTER SLAVE Send DAT_O() Receive DAT_I() Assert ACK_O Send DAT_O() Receive DAT_I() Assert ACK_O
  17. 17. Pipelined wishbone protocolPipelined wishbone protocol  The MASTER does not wait for [ACK_I] before putting the next address/data word on the bus  [STALL_I] asserted indicates slave can no longer accept another request  MASTER outputs requests as long as [STALL_I] is low 17 CLK_I CYC_O STB_O ACK_I STALL_I
  18. 18. Pipelined wishbone protocolPipelined wishbone protocol  Master does not wait for an ACK from the slave before sending next data 18 MASTER SLAVE Send multiple DAT_O() Without waiting for ACK_I Receive DAT_I() Begin sending ACKs
  19. 19. Use of TAG TYPESUse of TAG TYPES  The wishbone interface can be modified with user defined signals  Tags allow user defined information to be associated with an address, a data word or a bus cycle  The table below lists all user defined tag types 19 MASTER SLAVE Description TAG TYPE Associated with TAG TYPE Associated with Address tag TGA_O() ADR_O() TGA_I() ADR_I() Data tag, input TGD_I() DAT_I() TGD_I() DAT_I() Data tag, output TGD_O() DAT_O() TGD_O() DAT_O() Cycle tag TGC_O() Bus Cycle TGC_I() Bus Cycle

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