VHDL - Enumerated Types (Part 3)

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Lecture 12

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VHDL - Enumerated Types (Part 3)

  1. 1. Enumerated TypesThe first style is used most often to define cases or statesfor a state machinetype CAR_STATE is (back, stop, slow, medium, fast);VHDL also allows users to create subtypes of a type The values in the subtype must be a contiguous range of values of the base type from start to end Subtype GO_KART is CAR_STATE range stop to medium;VHDL has two predefined integer subtypes Subtype natural is integer range 0 to highest integer; Subtype positive is integer range 1 to highest integer; 1
  2. 2. Enumerated TypesBIT – can be ‘0’ or ‘1’ (note single quotes)STD_LOGIC IEEE std_logic_1164 package Has NINE legal values: ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’Example Subtype Declarations Subtype twoval_logic is std_logic range ‘0’ to ‘1’; Subtype fourval_logic is std_logic range ‘X’ to ‘Z’; Subtype negint is integer range -2147483647 to -1; Subtype bitnum is integer range 31 downto 0; 2
  3. 3. ConstantsThey contribute to readability, maintainability andportability of programs in any languageThe syntax is as shownconstant BUS_SIZE: integer := 32; -- width of componentconstant MSB: integer := BUS_SIZE - 1; -- bit number of MSBconstant Z: character := ‘Z’; -- synonym for Hi-Z value The value of a constant can be a simple expression Constants can be used anywhere the corresponding value can be used and they can be put to good use in type definitions 3
  4. 4. ArraysAnother very important category of user-defined typesOrdered set of elements of the same type, where each element isselected by an array indexSyntax for VHDL array definitionstype type-name is array (start to end) of element-type;type type-name is array (start downto end) of element- type;type type-name is array (range-type) of element-type;type type-name is array (range-type range start to end) of element-type;type type-name is array (range-type range start downto end) of element-type; 4
  5. 5. Array declarationstype monthly_count is array (1 to 12) of integer;type byte is array (7 downto 0) of STD_LOGIC;constant WORD_LEN: integer := 32;type word is array (WORD_LEN - 1 downto 0) of STD_LOGIC;constant NUM_REGS: integer := 8;type reg_file is array ( 1 to NUM_REGS ) of word;type traffic_light_state is (reset, stop, wait, go);type statecount is array (traffic_light_state) of integer; Array elements are considered to be ordered from left to right in the same direction as index range 5
  6. 6. Array declarationstype monthly_count is array (1 to 12) of integer; 1type byte is array (7 downto 0) of STD_LOGIC; 7Constant WORD_LEN: integer := 32;type word is array (WORD_LEN - 1 downto 0) of STD_LOGIC; 31Constant NUM_REGS: integer := 8;type reg_file is array ( 1 to NUM_REGS ) of word; 1Type traffic_light_state is (reset, stop, wait, go);type statecount is array (traffic_light_state) of integer; reset Left most elements of arrays are shown in blue 6
  7. 7. Array elements and literalsWithin VHDL program statements, individual array elementsare accessed using the array name and the element’s index inparentheses.If M, B, W, R, and S are signals of variables of the five arraytypes defined in the previous slides then M(11), B(5),W(WORD_LEN – 5), R(0,0), R(0) and S(reset) are all validelements.Array literals can be specified by listing the element values inparentheses. The byte variable B could be set to all ones by thestatementB := (‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’); 7
  8. 8. Array elements and literalsVHDL also has a shorthand notation that allows you to specifyvalues by index.To set word variable W to all ones except for zeroes in the LSBof each byteW := (0 => ‘0’, 8 => ‘0’, 16 => ‘0’, 24 => ‘0’, others => 1);The methods work for arrays with any element type, but theeasiest way to write a literal of type STD_LOGIC is to use a“string”VHDL string is an array of ISO characters enclosed in doublequotes such as “Hello” 8
  9. 9. StringA string is just an array of characters.A STD_LOGIC array of a given length can beassigned the value of a string of the same length, aslong as the characters in the string are taken from theset of nine characters defined as the possible values ofthe STD_LOGIC elements like ‘0’, ‘1’, ‘U’ The two previous examples can be rewritten asB := “11111111”;W := “11111110111111101111111011111110”; 9
  10. 10. Example: LogicFcn ports A B C Y entity architecture 10
  11. 11. Entity Declaration for LogicFcn library IEEE; use IEEE.std_logic_1164.all; entity LogicFcn is port ( A A: in std_logic; B Y B: in std_logic; C C: in std_logic; Y: out std_logic ); end entity LogicFcn; 11
  12. 12. Parts of Architecture Bodyarchitecture ARCH_NAME of ENTITY_NAME is <declarative section : list internal signals, variables, and components here. For each component used show the port map, (unless port map defined is in a “package”) >begin <statement section : all concurrent statements and components and processes in this section execute at the same time, NOT sequentially>end ARCH_NAME; 12
  13. 13. Architecture BodySpecifies the internal circuit of an entity, using any one of the following modeling styles:1. As a set of interconnected components, as wired (called structural modeling)2. As a set of concurrent signal assignment statements (called dataflow modeling)3. As a set of sequential assignment statements, i.e., a “process” (called behavioral modeling)4. As any combination of the above (called mixed modeling) 13
  14. 14. Architecture Body (Dataflow)With a signal assignment statement: architecture dataflow of LogicFcn is begin Y <= (not A and not B) or C; end dataflow; 14
  15. 15. Architecture Body (Dataflow)With a conditional signal assignment statement: architecture dataflow of LogicFcn is begin Y <= 1 when (A = 0 AND B = 0) OR (C = 1) else 0; end dataflow; 15
  16. 16. Architecture Body (Behavioral) architecture behavioral of LogicFcn is“Label:” begin Sensitivity List - The Process will be executed anytime there is anName of fcn: process (A,B,C) EVENT (change of state) on one ofprocess these signals. begin wait on A,B,C; WAIT ON statement - has same effect as sensitivity list. if (A = 0 and B = 0) then CANNOT USE BOTH. Processes with WAIT statements Y <= 1; cannot have sensitivity lists !! process elsif C = 1 then Y <= 1; Statements within Processes are executed sequentially. (This is a else single IF statement) The process, however, executes Y <= 0; concurrently with other processes and concurrent statements in the end if; architecture. end process; end behavioral; Values are assigned to signals when process suspends 16
  17. 17. Architecture Body (Structural)Internal signals are LOCAL to the Architecture, and cannotbe seen outside it ! signals notA A andSignal B notB C Y entity architecture 17
  18. 18. Architecture Body (Structural) architecture structural of LogicFcn is LOCAL SIGNALS areCOMPONENT signal notA, notB, andSignal: std_logic; declared within thedeclarations begin architecture and theymay go here i1: inverter port map (i => A, have no MODE (IN, OUT, etc.) o => notA); i2: inverter port map (i => B, o => notB); These are a1: and2 port map (i1 => notA, COMPONENT i2 => notB, INSTANTIATIONS y => andSignal); o1: or2 port map (i1 => andSignal, i2 => C, y => Y); end structural; 18
  19. 19. Components for Structural Model library IEEE; component OR2 port ( use IEEE.std_logic_1164.all; i1: in std_logic; package primitive is i2: in std_logic; component AND2 port ( y: out std_logic i1: in std_logic; ); i2: in std_logic; end component; y: out std_logic component INVERTER port ( ); i: in std_logic; end component; o: out std_logic ); end component; end primitive; these are component declarations 19

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