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- 1. Design a clocked synchronous state machinewhich accepts two serial strings of digits ofarbitrary length, starting with LSB andproduces the sum and carry of the two bitstreams as its output. The input bit streamscould come from two shift registers clockedsimultaneously . WhilePerforming addition there is a possibility of acarry being generated. This carry if generatedAssuming Moore care of while adding the nextshould be taken Machine DesignLSBLet the inputs be X and YLet the outputs be S and C
- 2. Obtaining the state DiagramAssume initial condition to be SC = 00Let the state be represented by state AIf XY = 00, then output SC = 00, Samestate A = 01, then output SC = 10, goes tostate B = 10, then output SC = 10, goes tostate B A 01,10 B 00 = 11,00 10 then output SC = 01, goes tostate C 11 C 01
- 3. Obtaining the state Diagram Assume machine has moved to state B If XY = 00, then output SC = 00, goes to state A = 01, then output SC = 10, same state B = 10, then output SC = 10, same state B 01,10 = 11, A B then output SC = 01, goes to 00 01,10 state C 00 00 10 11 11 C 01
- 4. Obtaining the state Diagram Assume machine has moved to state C If XY = 00, then output SC = 10, goes to state B = 01, then output SC = 01, same state C = 10, then output SC = 01, same state C = 11, A 01,10 B then output SC = 11, goes to 00 01,10 state D 00 00 10 11 11 C 00 11 D 01,10 01 11
- 5. Obtaining the state Diagram Assume machine has moved to state D If XY = 00, then output SC = 10, goes to state B = 01, then output SC = 01, goes to state C = 10, then output SC = 01, goes to A 01,10 B state C 01,10 00 = 11,00 00 10 then output SC = 11, same state D 11 11 00 C 00 11 D 01,10 11 01 11 01,10
- 6. Obtaining the state/output table State/output table State Input XY Output S 00 01 10 11 SC A A B B C 00 B A B B C 10 C B C C D 01 D B C C D 11 Next State S*
- 7. Assigning state variable to obtaintransition/output table Transition/output table State Input XY Output Q1Q0 00 01 10 11 SC 00 00 01 01 10 00 01 00 01 01 10 10 10 01 10 10 11 01 11 01 10 10 11 11Encoding A = 00, B = 01Next State Q1*Q0*C = 10, D = 11 Choosing D type flip flops
- 8. Constructing the excitation table Excitation/output table State Input XY Output Q1Q0 00 01 10 11 SC 00 00 01 01 10 00 01 00 01 01 10 10 10 01 10 10 11 01 11 01 10 10 11 11 D1D0
- 9. Transferring onto K-maps to derive excitationequations Excitation table State Input XY Q1Q0 00 01 11 10 00 0 0 1 0 01 0 0 1 0 11 0 1 1 1 10 0 1 1 1 D1 = X ⋅ Y + Q1 ⋅ X + Q1 ⋅ Y
- 10. Transferring onto K-maps to derive excitationequations Excitation table State Input XY Q1Q0 00 01 11 10 00 0 1 0 1 01 0 1 0 1 11 1 0 1 0 10 1 0 1 0 D 0 = X ⊕ Y ⊕ Q1
- 11. Output equations Excitation/output table State Input XY Output Q1Q0 00 01 10 11 SC 00 00 01 01 10 00 01 00 01 01 10 10 10 01 10 10 11 01 11 01 10 10 11 11 S = Q0 C = Q1
- 12. Circuit (logic) diagramD 0 = X ⊕ Y ⊕ Q1 D1 = X ⋅ Y + X ⋅ Q1 + Y ⋅ Q1 excitation equations S = Q0 C = Q1 output equations X Y Q1 D0 Q0 D Q S Q D1 D Q Q1 C Q Clk
- 13. Design a clocked synchronous state machine which outputs a logic ‘1’ whenever the input sequence 0101 is detected, and which outputs a ‘0’ otherwise . The input is supplied serially one bit at a time. The machine should also detect overlapping sequences as shown below. Input 001010100010100Assuming Mealy machine designOutput 000010100000100Let the input be X and output be Z
- 14. Obtaining the state Diagram Assume initial condition to be Z = 0 Let the initial state be represented by state A If X = 0, then output Z = 0, goes to state B = 1, then output Z = 0, Same state AX/Z 0/0 1/0 A B
- 15. Obtaining the state Diagram Assume machine has moved to state B If X = 0, then output Z = 0, Same state B = 1, then output Z = 0, goes to state CX/Z 0/0 1/0 A B 0/0 1/0 C
- 16. Obtaining the state Diagram Assume machine has moved to state C If X = 0, then output Z = 0, goes to state D = 1, then output Z = 0, goes to state AX/Z 0/0 1/0 A B 0/0 1/0 1/0 0/0 D C
- 17. Obtaining the state Diagram Assume machine has moved to state D If X = 0, then output Z = 0, goes to state B = 1, then output Z = 1, goes to state CX/Z 0/0 1/0 A B 0/0 1/0 1/0 0/0 0/0 D C 1/1
- 18. Obtaining the state/output table State/output table State Input X S 0 1 A B,0 A,0 B B,0 C,0 C D,0 A,0 D B,0 C,1 Next State S*, Z
- 19. Assigning state variable to obtaintransition/output table Transition/output table State Input X Q1Q0 0 1 Encodin 00 01,0 00,0 g A = 00 01 01,0 10,0 B = 01 C = 10 10 11,0 00,0 D = 11 11 01,0 10,1 Next State Q1*Q0*, ZChoosing D type flip flop
- 20. Constructing the excitation table Excitation/output table State Input X Q1Q0 0 1 00 01,0 00,0 01 01,0 10,0 10 11,0 00,0 11 01,0 10,1 D1D0, Z
- 21. Transferring onto K-maps to derive excitation & output equationsExcitation/output State Input X State Input Xtable Q1Q0 0 1 Q1Q0 0 1 State Input X 00 0 0 00 1 0 Q1Q0 0 1 01 0 1 01 1 0 00 01,0 00,0 11 0 1 11 1 0 01 01,0 10,0 10 1 0 10 1 0 10 11,0 00,0 D1 D0 11 01,0 10,1 D1 = Q0 ⋅ X + Q1⋅ Q0 ⋅ X D0 = X D1D0, Z
- 22. Transferring onto K-maps to derive excitation & output equationsExcitation/output State Input Xtable Q1Q0 0 1 State Input X 00 0 0 Q1Q0 0 1 01 0 0 00 01,0 00,0 11 0 1 01 01,0 10,0 10 0 0 10 11,0 00,0 Z 11 01,0 10,1 Z = Q1⋅ Q 0 ⋅ X D1D0, Z
- 23. Circuit (logic) diagram D0 = X D1 = Q0 ⋅ X + Q1⋅ Q0 ⋅ X excitation equation Z = Q1⋅ Q 0 ⋅ X output equations X X Q0 Q0 Q1 Z D0 Q0 D Q Q D1 D Q Q1 QClk

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