Flip chip market technology trends 2013 Report by Yole Developpement


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Cu pillar and µbumping for memory, consumer electronics and mobile phones have reinvigorated the Flip-Chip market, enabling it to grow at a 19% rate and cater to the most advanced technologies, like 3DIC and 2.5D

Despite its high 19% CAGR, Flip-chip is not new -- in fact, it was first introduced by IBM over 30 years ago! As such, it would be easy to consider it an old, uninteresting, mature technology…but this is far from true! Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3DIC and 2.5D. Indeed, no matter what packaging technology you're using, a bumping step is always required at the end!
In 2012, bumping technologies accounted for 81% of the total installed capacity in the middle-end area. That's big. Really big. So big that it represents 14M+ 12’’eq wafers (2012 installed capacity: see figure below) -- and fab loading rates are high as well, especially for the Cu pillar platform (88%). Flip-Chip is also big on value: in 2012 it was a $20B market (making it the biggest market in the middle-end area), and we expect it to continue growing at an 9% clip, ultimately reaching $35B by 2018!

Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:
1) CMOS 28nm IC, including new applications like APE and BB;
2) The next generation of DDR Memory;
3) 3DIC/2.5D Interposer using µbumping. Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.

Key features
- Fully updated 2010 - 2018 market forecast and bottom-up approach, including micro-bumping for 3DIC!
- 2012 installed capacity
- Comparison between C2 and TCB
- Strong focus on micro-bumping for 3DIC & 2.5D
- Market share/data for Flip-Chip bonder
- Detailed technology roadmap
- TIM market data
- Application focus: HB-LED, CIS, µbumping for 3DIC and 2.5D, memory, analog, RF, mixed signals IC
- Underfill market data
- Flip-Chip substrate market data

More information at http://www.i-micronews.com/reports/Flip-Chip-Market-Trends/8/353/
Review the recorded video of the Flip-Chip webcast at http://www.i-micronews.com/consult_webcast.asp?uid=126

Published in: Technology

Flip chip market technology trends 2013 Report by Yole Developpement

  1. 1. FLIP-CHIP Market and Technology Trends 2013 Business Update Flip Chip platform is still in mutation and provides continuously innovative fine pitch bumping solutions to serve the most advanced packaging technologies like 3DIC and 2.5D Interposer !© 2013
  2. 2. Table of contents (1/3)• Table of contents ………………………………………………………… 2• Glossary …………………………………………………………………… 5• Report Scope …………………………………………………………….. 6 – What’s new ? 7 – Report technology scope 10 – Report objectives 15 – Companies cited in the report 17• Executive summary ……………………………………………………... 18 – General conclusions 19 – Flip-Chip market in 2012 21 – Flip-Chip market in 2018 22• Recent key press headlines …………………………………………… 64• Flip-Chip market forecast 68 – Methodology 69 – Flip-Chip Activity – Wafer forecast 72  By metallurgy type 72  By area and end products 80 – Flip-Chip Activity – Unit forecast 91 © 2013 • 2 Copyrights © Yole Développement SA. All rights reserved.
  3. 3. Table of contents (2/3)• Flip-Chip installed capacities …………………………………………. 95 – Methodology 97 – 2012 installed capacities 98 – Recent activity and investments for FC 108 – Focus on PTI’s recent investment 109 – Matching 2012 top down and bottom up 119 – Summary 120• Flip-Chip market value ………………………………………………….. 122 – Flip-Chip Market Value Forecast 123 – 2012 total Flip-Chip Market Value by COO segment 124 – 2012 total Flip-Chip Market Value by end use type 126 – 2012 Flip-Chip in package Market Value by COO segment 127 – 2018 total Flip-Chip Market Value by COO segment (forecast) 128• Infrastructure & supply chain …………………………………………. 130 – Transforming golbal IC Packaging Supply Chain* 131 – Flip-Chip Supply Chain 133 – Typical Flip Chip Flow-Chart 134 – Flip Chip Supply Chain Ecosystem 135 – Business Model in Flip Chip Space 136 – Flip Chip Players 137 – Business cases and supply chain examples 139 © 2013 • 3 Copyrights © Yole Développement SA. All rights reserved.
  4. 4. Table of contents (3/3)• Bumping technologies …………………………………………………... 146 – Overview of bumping technologies 148 – Focus on Cu pillar bumping 157 – µ-bumping for 2.5D/3DIC 172 – C2 & TCB – applications and trends 204• Assembly technologies …………………………………………………. 215 – Substrates 216 – Flip-Chip bonders 230 – TIM 237 – Underfills 245• Flip-Chip applications & market ……………………………………….. 255 – Memories 260 – Imaging 272 – 2D Logic SoC 275 – HB-LED 287 – Small logic, RF, Power, Analog and mixed signals ICs 298 – µ-bumping for 2.5D & 3D SiP/SoC 310• Conclusions & Perspectives …………………………………………… 323• Presentation of Yole’s Activity ………………………………………… 328 © 2013 • 4 Copyrights © Yole Développement SA. All rights reserved.
  5. 5. A 2013 business update including µ-bumping ! and many more new features…• “Flip-Chip 2011” report was the first Yole’s report dedicated to the flip-chip platform, its related bumping technologies and applications• This 2013 version provides an update of all the major parts describing this advanced packaging technological platform (market forecast, supply chain, technology trends and applications)• Major changes and improvements – The new Yole’s top down approach has been used, leading to an exhaustive quantification of IC devices using flip-chip (80 IC screened, in 90 end products and 9 markets) leading to a more accurate modeling of the flip-chip market – In the frame of this new top down approach, major changes and improvements have to be highlighted • Flip-Chip micro-bumping has been included in this update to point out the impact of the brand new technological platforms (3DIC, 2.5D Interposer) driving new demand of FC copper pillar • Accurate modeling of memory and HB-LED applications © 2013 • 5 Copyrights © Yole Développement SA. All rights reserved.
  6. 6. Also new in this 2013 report…• Market analysis – Fully updated 2010 – 2018 market forecast – Fully updated bottom up approach • 2012 installed capacities • 2010 – 2014 capacity expansion overview• Technology analysis – Comparison between C2 and TCB – Strong focus on micro-bumping for 3DIC & 2.5D – Updated and new parts on assembly • TIM (new) • Flip-chip bonders (new) • Underfills • Substrates• Applications – Flip-chip for HB-LED – Micro-bumping in 3DIC and 2.5D Interposer applications – Flip-chip for memories – Flip-chip for analog, RF, mixed signals IC© 2013 • 6 Copyrights © Yole Développement SA. All rights reserved.
  7. 7. What we highlighted, what we missed in our 2011 Flip-Chip report• 2011 Flip-Chip was the first Yole’s report on Flip-Chip technology, thus completing our report collection describing wafer level packaging infrastructure• What we chose not to address – Thermal Interface Materials – Silicon to silicon Micro-bumping – but we mentioned it would be included in this new release – High Power LEDs since it was an emerging market with specific technologies  these 3 topics have been included in this new report• What we missed – Flip-Chip adoption for memory, faster than expected• What we highlighted / we pointed out – Our CAGR, wafer forecast, unit forecast and revenues forecast have been in good agreement with 2011/2012 production – We expected a wide adoption of Cu pillar for APE, BB and advanced CMOS ICs – We mentioned that Copper Pillar Bumping was on its way to become the next standard solution for flip chip bumping – Moreover, we concluded that “by largely contributing to the consolidation of the “middle-end” wafer level packaging infrastructure, flip chip will favor the fast growth of 3D wafer level packaging with through silicon vias (which require a similar infrastructure) and will benefit from it in return (fast growth of silicon to silicon micro-bumping, emergence of silicon and glass interposers in flip chip packages)” © 2013 • 7 Copyrights © Yole Développement SA. All rights reserved.
  8. 8. Wafer Bumping Packaging and Applications Definition WAFER BUMPING FLIP CHIP WAFER LEVEL PACKAGING Chip on Board Silicon on silicon CHIP FC BGA FC CSP COF/COG micro-bumping FAN IN FAN OUT EMBEDDINGBump Bump Bump Bump Bump characteristicscharacteristics characteristics characteristics characteristics Ball droppingPlating, screen Plating, screen Plating Plating pitch: 400-500µmprinting printing, stud pitch: <150µm pitch: < 60µmpitch: <180µm pitch: < 150µm Courtesy of Statschippac Courtesy of 3M Courtesy of NXP and FCI Courtesy of SPIL Scope of the 2012 Scope of the 2012 Scope of the WLCSP report fan-out/embedded report 2013 Flip-Chip report© 2013 • 8 Copyrights © Yole Développement SA. All rights reserved.
  9. 9. Report Objectives• The objectives of this report are – To update the business status of the Flip-Chip market – To provide a forecast for the next five years, and predict future trends – To provide an overview of the technological trends and applications that use Flip-Chip technology• The Flip-Chip market is studied from the following angles – Market forecast (demand, production and installed capabilities) – Industrial supply chain – Market drivers – Market value – State-of-the-art technology and trends – End-user applications © 2013 • 9 Copyrights © Yole Developpement SA. All rights reserved.
  10. 10. Company cited in the report3M, AdvanPack Solutions, AEM Tec, Ajinomoto, Akita, Altera, AMD, Amkor, Apple, Applied Materials, ASE, Asymtek, Bergquist, Carsem, Casio Micronics, Chipbond, Chipmos, Chomerics, Cookson, Dalsa, Datacon, Dek, Denka, Dow Chemical, Dow Corning, Elpida, EMMicroelectronics, Epcos, eSilicon, FCI, Fraunhofer IZM, Fuji Polymer, Fujitsu, Global Foundries, Global Unichip, Henkel, Hitachi Chemical, Honeywell, Ibiden, IBM, IC interconnect, IMI, Indium Corporation, Infineon, Intel, Ipdia, JCAP, J-devices, Kinsus, Kyocera, LB Semicon, Lord Corporation, Lumileds, Micrel, Minami, Murata, Namics, Nanium, Nan Ya, Nepes, Nexx, Nichia, Nokia, Nordson, Nvidia, NXP, OKI, Omnivision, Optopac, OSE, Pactech, Panasonic, Polymatech, PowerTech (PTI), Premier Semiconductor Services, Qualcomm, Renesas, Samsung, Samsung Electromechanics (SEMCO), Shibuya, Shin Etsu, Shinko Electric, Silex Microsystems, Siltech, Sony Chemical, SPIL, StatsChipPac, SK-Hynix, STMicroelectronics, Sumitomo, TDK, Tessera, Texas Instruments, Tong Hsing, Toray, Toshiba, Triquint, TSMC, UMC, Unimicron, Unisem, UTAC, Xilinx, Zymet and more…© 2013 • 10 Copyrights © Yole Developpement SA. All rights reserved.
  11. 11. Flip-Chip market in 2012… $20B 20B 12.8M Taiwan 50% Market Units 12’’eq wafer #1 Location End Product• In 2012… – Flip-Chip was a $20B market – 20 M units ICs have been bumped (12.8M 12’’eq wafers) – Average fab loading rate was 78% – Taiwan became the leading place for flip-chip bumping – 50% of bumped wafers were used in a laptop or a desktop – IC which are flip-chip packaged can be classified in 2 categories  Early adopters like GPU, CPU and Chipset that have been using FC for a long time  New comers like interposer IC, memory, APE, BB, that are moving fast to flip chip mainly motivated by the ultra fine pitch, the high IO count possibility and the provided performance of this interconnection solution© 2013 • 11 Copyrights © Yole Développement SA. All rights reserved.
  12. 12. Flip-Chip drivers and benefits• Drivers and benefits provided by Flip-Chip – High I/O density  APE, BB in fcCSP – Large die-to-package fan-out area  GPUs, CPUs, chipsets in fcBGA – Interconnection to fine-pitch substrate  Display drivers in COG, COF – Electrical performance / interface bandwidth  In particular for APE, GPUs, FPGAs, ASICs, PMU, RF Tx, memories – Thermal dissipation  CPUs, GPUs, PA – Hermeticity  SAW filters – Ergonomics, topology  CMOS Image Sensors and LEDs © 2013 • 12 Copyrights © Yole Développement SA. All rights reserved.
  13. 13. Flip-Chip wafer forecast by bumping metallurgy *3D µ-bumping included Flip-chip bumping wafer forecast* Breakdown by bumping metallurgy (12eq wafers) Yole Developpement © February 2013 Cu Pillar 2010 – 2018 Flip-Chip CAGR = 19% Lead Free Solder Sn/Pb Eutectic Solder Gold Stud + Plated 2010 2011 2012 2013 2014 2015 2016 2017 2018© 2013 • 13 Copyrights © Yole Développement SA. All rights reserved.
  14. 14. Flip-Chip wafer forecast by bumping metallurgy Comments• Cu Pillar is already a well established platform, especially due to Intel that started Cu pillar bumping of processors in 2006• This technology diffused during the 7 last years within the industry and today, the important expected growth of Cu pillar bumping (35% CAGR on the 2010 – 2018 time frame) is mainly linked to the big demand coming from 3 areas – CMOS 28nm IC (and beyond), including new types of ICs like Application Processors (APE), Base Band module (BB) for mobile phones – Next generation of DDR Memories (DDR3 and DDR4 memories) – 3DIC/2.5D Interposer using Cu pillar (µbumping)• µbumping for 3DIC and 2.5D Interposer is a real game changer for the packaging industry and we decided to include it in our updated market forecast to highlight how it will impact the flip-chip landscape © 2013 • 14 Copyrights © Yole Développement SA. All rights reserved.
  15. 15. 2012 Flip-Chip wafer start By end product 2012 Flip-Chip wafer start* Breakdown by end product (12eq wafers) *3D µ-bumping included Tablet 212 999 Set-Top Box and Hybrid 2% Set-Top Box Server Network (Switch, Router, 177 625 172 784 Appliance) 1% 1% Base stations 298 779 180 327 2% Other end applications 2% Game stations 270 474 504 135 2% 4% Laptop 3 662 163 Feature Phone 29% 555 129 4% Desktop PC Screen 590 940 5% HPC 791 256 6% Desktop PC Smartphones 2 695 375 1 163 752 Smart TV & LCD TV 21% 9% 1 491 188 12% Yole Developpement © February 2013• In 2012, Laptop and desktop PC were the top end products using Flip Chip• PCs are followed by Smart TV and LCD TVs (for LCD drivers), smartphones and high performance computers © 2013 • 15 Copyrights © Yole Développement SA. All rights reserved.
  16. 16. Wafer Bumping Trends Pitch capabilities / Alloy• Bumping interconnect technology roadmap for FC BGA 160 Flip Chip Screen Printing Array 140 solder bump conductive polymer bump 120 Micro-bump Flip Chip Peripheral bonding 100 Pitch (µm) Electroplating / Evaporation / Stud bumping 80 Au bump Bump-less Solder bump ‘pads’? 60 Cu-pillars 45 nm 40 Electroplating Cu-Pillars µ-Bumps 32 nm 20 22 nm 18 nm 0 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 Eutectic, High Lead, Pb free Lead free, Au stud, Solder bump, Cu pillars (SnAgCu) © 2013 • 16 Copyrights © Yole Développement SA. All rights reserved.
  17. 17. Bumping Hierarchy * in Flip Chip & related 3D Packaging Solutions as of 2013* in pitch (µm), underfills not represented µ-Bumps: 10-40µm Wide I/O memory stack µ-Bumps 20-80µm Digital IC CPU 2.5D Silicon interposer Bumps/Cu Pillars: 40-250µm BGA Laminate 400-800µm PCB• µ-bumping for 2.5D & 3DIC in conjunction with new applications like APE, DDR memories etc. is going to boost flip-chip demand, thus leading also to new challenges and new technological developments. Today flip-chip is available through a wide range of pitches to answer specific needs of all the applications – µ-bumping for advanced 3D stacking: 10 – 20 µm pitch required – CMOS 28nm and below, logic on interposer etc.: 20 – 80 µm pitch required – Other logic (in FC BGA) : 40 – 450 µm pitch required © 2013 • 17 Copyrights © Yole Développement SA. All rights reserved.
  18. 18. Present/future markets for Flip-Chip Military & Aerospace Medical Cars devices HPC Servers Medical Lower Volumes Network Automotive Industrial Base stations Consumer Mobile & Consumer Set top box High Volumes Computing Smartphones/ Game stations tablets Smart TV/Display Desktop & Laptop• Flip-Chip technology is already present in a wide range of application, from high volumes/consumer applications, to low volumes/high end applications. All these applications have their own requirements, specifications and challenges ! © 2013 • 18 Copyrights © Yole Développement SA. All rights reserved.
  19. 19. About the Author of This Report Lionel Cadix – Lionel joined Yole after completing several projects linked to the characterization and modeling of high-density TSV and 3DIC chip stacking in collaboration with CEA-Leti and STMicroelectronics for his PhD. He is the author of several publications and holds eight patents in the field of 3D Integration Contact: cadix@yole.fr© 2013 • 19 Copyrights © Yole Developpement SA. All rights reserved.