Lect14

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Lect14

  1. 1. Virtual Memory 1
  2. 2. Memory Management Unit (or TLB)The position and function of the MMU 2
  3. 3. Virtual Address Space 15 14 Paging 13• Virtual Memory 12 • Physical Memory – Divided into equal- sized pages 11 – Divided into – A mapping is a 10 equal-sized translation between 9 frames • A page and a frame 8 • A page and null – Mappings defined at 7 1 7 runtime 6 12 6 • They can change 5 10 5 – Address space can 4 have holes 4 – Process does not 3 2 3 have to be 2 2 contiguous in 1 3 1 Physical Address physical memory 3 0 11 0 Space
  4. 4. Virtual Address Space 15 Typical AddressKernel 14 13 Space Layout 12 • Stack region is at top, 11 and can grow down Stack 10 • Heap has free space to Shared 9 grow up Libraries • Text is typically read-only 8 BSS 7 • Kernel is in a reserved, (heap) 6 protected, shared region 5 • 0-th page typically not Data 4 used, why? 3 Text 2 (Code) 1 4 0
  5. 5. Virtual Address Programmer’s perspective: Space 15 logically present 14 System’s perspective: Not 13 mapped, data on disk• A process may 12 be only partially 11 4 resident 10 14 6 – Allows OS to 9 2 store individual 8 10 pages on disk 7 1 Disk – Saves memory 6 15 for infrequently used data & code 5 4• What happens if 3 5 we access non- 2 resident 1 3 Physical Address memory? 0 13 Space 5
  6. 6. Proc 1 Address Proc 2 Address Space Space 15 15Currentlyrunning 14 14 13 13 12 Physical 12 Address Space 11 11 10 2 10 15 9 4 9 14 14 8 13 8 2 3 7 4 7 15 1 6 1 6 5 2 5 Disk 4 3 4Memory 3 13 3Access 2 2 1 1 6 0 0
  7. 7. Page Faults• Referencing an invalid page triggers a page fault • An exception handled by the OS• Broadly, two standard page fault types – Illegal Address (protection error) • Signal or kill the process – Page not resident • Get an empty frame • Load page from disk • Update page (translation) table (enter frame #, set valid bit, etc.) • Restart the faulting instruction 7
  8. 8. Virtual Address Space 15 6 14 Page 13 Table 0• Page table for 12 resident part of 11 address space 10 9 8 7 1 7 6 15 6 5 5 5 3 4 4 4 3 5 3 1 2 2 2 1 3 1 Physical 7 8 0 13 0 Address Space
  9. 9. • Note: Some implementations store disk block numbers of non-resident pages in the page table (with valid bit Unset) 9
  10. 10. Shared Pages• Private code and data • Shared code – Each process has own – Single copy of code copy of code and data shared between all – Code and data can processes executing it appear anywhere in – Code must not be self the address space modifying – Code must appear at same address in all processes 10
  11. 11. Proc 1 Address Proc 2 Address Space Space 15 15 14 140 13 13 5 12 Physical 12 Address Space 11 11 10 2 10 9 6 9 8 13 8 7 4 7 Two (or more) processes 6 3 6 running the 5 1 5 same program 4 3 4 4 and sharing 131 the text section 3 37 2 2 72 Page 1 1 Page 2 Table 0 0 Table 11
  12. 12. Page Table Structure• Page table is (logically) an array of 5 frame numbers – Index by page number• Each page-table entry (PTE) also has other bits 4 7 Page 2 Table 12
  13. 13. PTE bits• Present/Absent bit – Also called valid bit, it indicates a valid mapping for the page• Modified bit – Also called dirty bit, it indicates the page may have been modified in memory• Reference bit – Indicates the page has been accessed• Protection bits – Read permission, Write permission, Execute permission – Or combinations of the above• Caching bit – Use to indicate processor should bypass the cache when accessing memory • Example: to access device registers or memory 13
  14. 14. Address Translation• Every (virtual) memory address issued by the CPU must be translated to physical memory – Every load and every store instruction – Every instruction fetch• Need Translation Hardware• In paging system, translation involves replace page number with a frame number 14
  15. 15. virtual memory virtual and physical mem chopped up in pages• programs use virtual addresses• virtual to physical mapping by MMU -first check if page present (present/absent bit) -if yes: address in page table form MSBs in physical address -if no: bring in the page from disk page fault
  16. 16. Page Tables• Assume we have – 32-bit virtual address (4 Gbyte address space) – 4 KByte page size – How many page table entries do we need for one process? 17
  17. 17. Page Tables• Assume we have – 64-bit virtual address (humungous address space) – 4 KByte page size – How many page table entries do we need for one process?• Problem: – Page table is very large – Access has to be fast, lookup for every memory reference – Where do we store the page table? • Registers? • Main memory? 18
  18. 18. Page Tables• Page tables are implemented as data structures in main memory• Most processes do not use the full 4GB address space – e.g., 0.1 – 1 MB text, 0.1 – 10 MB data, 0.1 MB stack• We need a compact representation that does not waste space – But is still very fast to search• Three basic schemes – Use data structures that adapt to sparsity – Use data structures which only represent resident pages – Use VM techniques for page tables (details left to extended OS) 19
  19. 19. Two-level Page Table• 2nd –level page tables representing unmapped pages are not allocated – Null in the top-level page table 20
  20. 20. Two-level Translation 21
  21. 21. Example Translations 22
  22. 22. Alternative: Inverted Page TablePID VPN offset Index PID VPN ctrl next Hash Anchor Table 0 (HAT) 1 Hash 2 3 4 5 6 … IPT: entry for each physical frame
  23. 23. Alternative: Inverted Page TablePID VPN offset 0 0x5 0x123 Index PID VPN ctrl next Hash Anchor Table 0 (HAT) 1 Hash 2 1 0x1A 0x40C … 0x40C 0 0x5 0x0 0x40D 2 … … ppn offset 0x40C 0x123
  24. 24. Inverted Page Table (IPT)• “Inverted page table” is an array of page numbers sorted (indexed) by frame number (it’s a frame table).• Algorithm – Compute hash of page number – Extract index from hash table – Use this to index into inverted page table – Match the PID and page number in the IPT entry – If match, use the index value as frame # for translation – If no match, get next candidate IPT entry from chain field – If NULL chain entry ⇒ page fault 25
  25. 25. Properties of IPTs• IPT grows with size of RAM, NOT virtual address space• Frame table is needed anyway (for page replacement, more later)• Need a separate data structure for non-resident pages• Saves a vast amount of space (especially on 64-bit systems)• Used in some IBM and HP workstations 26
  26. 26. Given n processes• how many page tables will the system have for – ‘normal’ page tables – inverted page tables?
  27. 27. Another look at sharing…
  28. 28. Proc 1 Address Proc 2 Address Space Space 15 15 14 140 13 13 5 12 Physical 12 Address Space 11 11 10 2 10 9 6 9 8 13 8 7 4 7 Two (or more) processes 6 3 6 running the 5 1 5 same program 4 3 4 4 and sharing 131 the text section 3 37 2 2 72 Page 1 1 Page 2 Table 0 0 Table 29
  29. 29. VM Implementation Issue• Problem: – Each virtual memory reference can cause two physical memory accesses • One to fetch the page table entry • One to fetch/store the data ⇒Intolerable performance impact!! ⇒• Solution: – High-speed cache for page table entries (PTEs) • Called a translation look-aside buffer (TLB) • Contains recently used page table entries • Associative, high-speed memory, similar to cache memory • May be under OS control (unlike memory cache) 30
  30. 30. On-CPUhardwaredevice!!! TLB operation Data structure in main memory 31
  31. 31. Translation Lookaside Buffer• Given a virtual address, processor examines the TLB• If matching PTE found (TLB hit), the address is translated• Otherwise (TLB miss), the page number is used to index the process’s page table – If PT contains a valid entry, reload TLB and restart – Otherwise, (page fault) check if page is on disk • If on disk, swap it in • Otherwise, allocate a new page or raise an exception 32
  32. 32. TLB properties• Page table is (logically) an array of frame numbers• TLB holds a (recently used) subset of PT entries – Each TLB entry must be identified (tagged) with the page # it translates – Access is by associative lookup: • All TLB entries’ tags are concurrently compared to the page # • TLB is associative (or content-addressable) memory 33
  33. 33. TLB properties• TLB may or may not be under direct OS control – Hardware-loaded TLB • On miss, hardware performs PT lookup and reloads TLB • Example: x86, ARM – Software-loaded TLB • On miss, hardware generates a TLB miss exception, and exception handler reloads TLB • Example: MIPS, Itanium (optionally)• TLB size: typically 64-128 entries• Can have separate TLBs for instruction fetch and data access• TLBs can also be used with inverted page tables (and others) 34
  34. 34. TLB and context switching• TLB is a shared piece of hardware• Normal page tables are per-process (address space)• TLB entries are process-specific – On context switch need to flush the TLB (invalidate all entries) • high context-switching overhead (Intel x86) – or tag entries with address-space ID (ASID) • called a tagged TLB • used (in some form) on all modern architectures • TLB entry: ASID, page #, frame #, valid and write-protect bits 35
  35. 35. TLB effect• Without TLB – Average number of physical memory references per virtual reference =2• With TLB (assume 99% hit ratio) – Average number of physical memory references per virtual reference = .99 * 1 + 0.01 * 2 = 1.01 36
  36. 36. Recap - Simplified Components of VM SystemVirtual Address Spaces Page Tables for 3 (3 processes) processes Frame Table 132 CPU TLB 1 2 3 Frame Pool Physical Memory 37
  37. 37. Recap - Simplified Components of VM SystemVirtual Address Spaces (3 processes) Inverted Page Table CPU TLB 1 2 3 Frame Pool Physical Memory 38
  38. 38. MIPS R3000 TLB• N = Not cacheable • V = valid bit• D = Dirty = Write protect • 64 TLB entries • Accessed via software through• G = Global (ignore ASID Cooprocessor 0 registers in lookup) – EntryHi and EntryLo 39
  39. 39. 0xFFFFFFFF R3000 Address kseg2 Space Layout 0xC0000000• kuseg: kseg1 – 2 gigabytes 0xA0000000 – TLB translated (mapped) – Cacheable (depending on ‘N’ bit) kseg0 – user-mode and kernel mode 0x80000000 accessible – Page size is 4K kuseg 40 0x00000000
  40. 40. 0xFFFFFFFF R3000 Address kseg2 Space Layout 0xC0000000– Switching processes kseg1 switches the translation 0xA0000000 (page table) for kuseg kseg0 0x80000000 Proc 1 Proc 2 Proc 3 kuseg kuseg kuseg 41 0x00000000
  41. 41. 0xffffffff R3000 Address kseg2 Space Layout 0xC0000000• kseg0: kseg1 – 512 megabytes 0xA0000000 – Fixed translation window to physical memory kseg0 • 0x80000000 - 0x9fffffff virtual = 0x80000000 0x00000000 - 0x1fffffff physical • TLB not used – Cacheable – Only kernel-mode accessible – Usually where the kernel code is placed kuseg Physical Memory 42 0x00000000
  42. 42. 0xffffffff R3000 Address kseg2 Space Layout 0xC0000000• kseg1: kseg1 – 512 megabytes 0xA0000000 – Fixed translation window to physical memory kseg0 • 0xa0000000 - 0xbfffffff virtual = 0x80000000 0x00000000 - 0x1fffffff physical • TLB not used – NOT cacheable – Only kernel-mode accessible – Where devices are accessed (and boot ROM) kuseg Physical Memory 43 0x00000000
  43. 43. 0xffffffff R3000 Address kseg2 Space Layout 0xC0000000• kseg2: kseg1 – 1024 megabytes 0xA0000000 – TLB translated (mapped) – Cacheable kseg0 0x80000000 • Depending on the ‘N’-bit – Only kernel-mode accessible – Can be used to store the virtual linear array page table kuseg 44 0x00000000

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