1. USHASREE KOTTA
Email ID: ushasreeg04@gmail.com Contact No: 08008400955
CAREER OBJECTIVE
Seeking a challenging career opportunity in a reputed organization which can utilize my
skills and helps me to advance my career by providing a competitive work environment with
continuous learning opportunities.
WORK EXPERIENCE
Company Name: Synapse design with Juniper Networks (9th June 2015 to current)
Designation: Project Engineer, Physical Design
PROFESSIONAL TRAINING
Training in Physical Design from Institute Of Silicon Systems Pvt Ltd, Hyderabad.
Duration: Nov 2014 to May 2015
CORE COMPETENCY
• Good Knowledge of ASIC flow and the stages involved in physical design flow.
• Have hands on experience in 16/45 node technologies
• Have excellent knowledge and hands on experience working with floorplan,
placement, clock tree synthesis, routing and optimization.
• Good Knowledge in understanding and resolving timing violations (hold and setup) of
various timing paths under OCV.
• Understanding of DFM Reliability issues like EM, Cross-talk, and Antenna effect.
• Ability to debug DRC and LVS errors (PG shorts, opens and soft checks) at block
level.
• Exposure to industry standard EDA tools like RTL Compiler, SOC Encounter, and
Encounter Timing System from Cadence.
• Ability to design a layout with good floor plan, optimized area, reducing parasitics.
• Good knowledge of IC fabrication process, CMOS concepts and Circuit theory, Digital
Design concepts.
EDUCATION
Degree Institution Percentage/CGPA
M.Tech (VLSI) (2011-2013) VIT University-Vellore,India 76.2
B.Tech (EIE)(2006-2010) Bhoj Reddy Engg College for 63.87%
Women(BRECW)-
Hyderabad, India
Intermediate(10+2)(2006- Narayana Junior College- 87.1%
2005) Hyderabad
Secondary (S.S.C.)(2004) Nalanda Vidya Bhavan High 86 %
School-Hyderabad, India

2. Ushasree Kotta
Email ID: ushasreeg04@gmail.com Contact No: 08008400955
TECHNICAL PROFICIENCY
• Skill set: Physical Design, Logical Synthesis, Physical Verification, LEC
• EDA Tools and other tools: SOC Encounter, ICC2 , PT, Cadence Virtuoso,
Cadence Layout Editor, Quartus II-Altera, Quartus II-Model Sim
• Domain Specific: Place & Route and Sign-off
• Scripting Languages: TCL
• Languages: Verilog HDL, Basics of C
PHYSICAL DESIGN PROJECTS
Project Project 1 – Block Level
Client Juniper Networks
Role • Responsible for performing Floor planning to Routing along with
STA and eco analysis on the design using the Juniper Flow.
• Fix the DRC’s on Base and Metal layers (M2 to M12).
• Fix the power (PG) short issues between VDD & VDDM & VSS
nets.
• Move the cells away from the power network (VIA34) & do Eco
route.
• Fix the opens & shorts on clk & signal nets.
Description • Technology – 16nm
• Gate Count : 200K
• Max Frequency of Operation : 1 GHz
• Maximum number of Layers used in the design : 12
Tools: SOC Encounter, Calibre.
Project Project 2 – Block Level
Client Juniper Networks
Role • Responsible for performing Floor planning to Routing along with
STA and eco analysis on the design using the Juniper Flow .
• Physical Verification (DRC, LVS) has also been done with DRC’s
and LVS errors were fixed.
• Fixed Timing violations because of using large no. of HVT’s in our
design, reduced it by VT Swapping.
Description • Technology – 16nm
• Gate Count : 1.8 M
• Number of Clocks in the design : 1
• Max Frequency of Operation : 1 GHz
• Maximum number of Layers used in the design : 12
Tools: SOC Encounter, Calibre.

3. USHASREE KOTTA
Email ID: ushasreeg04@gmail.com Contact No: 08008400955
Project : 3 Network Chip
Client Juniper Networks
Technology 16nm
Block Names Repeaters & Feedthrus
Technology &ToolsICC2 Compiler
Role Physical Verification (DRC, LVS)
Responsibilities • Fix the DRC’s on Metal layers (M2 to M12).
• Fix the Base violations like Vth & LUP.
• Do the check legality to fix any overlapping cells issues.
• Fix the power short issues between VDD & VDDM nets.
• Fix the clock spines overlapping shorting issues on M4 & M5.
• Move the cells away from the power network & do Eco route.
• Fixing the opens & shorts signal nets.
Project 4 Block Level Implementation 45 nm
Role Performing Audit checks, Design Import, Floor Plan, Power Plan,
Placement, Trial Route, IPO, CTS, Detailed Routing, Timing Analysis,
Physical Verification (DRC, LVS)
Description • Gate Count : 1074460
• Number of Clocks in the design : 6
• Max Frequency of Operation : 0.22 GHz
• Number of Macros in the design : 2
• Maximum number of Layers used in the design : 6
• Clock Tree Synthesis has been performed by generating a Clock
Specfile with the given specifications to meet the target skew
• Generated DRC and LVS were fixed
Tools: SOC Encounter.
Project 5 Block Level Implementation 130 nm
Role Performing Audit checks, Design Import, Floor Plan, Power Plan,
Placement, Trial Route, IPO, CTS, Detailed Routing, Timing Analysis,
Physical Verification (DRC, LVS)
Description • Number of clocks in the design : 17
• Max Frequency of Operation : 0.2 GHz
• Number of Macros in the design : 12
• Maximum number of Layers used in the design : 5
• Sign off Timing and ECO's were performed
Tools: SOC Encounter, ETS.
Project 7 Custom Layout 130 nm
Role Drawing Stick Diagrams, creating Layouts, running DRC and LVS

4. escription Created Layouts for different standard cells (NAND, NOR, OR, AND,
INVERTER) and 5x5 matrix of these standard cells were designed for
which DRC and LVS check has been performed
Tools: Cadence Layout Editor
USHASREE KOTTA
Email ID: ushasreeg04@gmail.com Contact No: 08008400955
PAPERS PUBLISHED AND CONFERENCES ATTENDED
• Presented and published a paper titled “VLSI Implementation of Single Precision Floating
Point Unit using Verilog” in 2013 IEEE conference on information and Communication
Technologies (ICT 2013) held during 11th
and 12th
April 2013,organised by Noorul
Islam Centre for Higher Education, Tamil Nadu, India.
• Presented a paper titled “ASIC implementation of space wire router IP protocol for
space wire applications” at 4rth international science and engineering technology
(SET) conference organized by VIT University, Vellore,Tamilnadu, India.
ACTIVITIES AND ACHIEVEMENTS
• Organizes and volunteering for rural education, Soft skills development, social
awareness and responsibility events.
• Organizes and participates in many other social activities like maintaining hygienic
environment at government hospitals, schools, old age homes…etc
• Event organizer in school annual day functions and other technical events.
• School head for social services committee and raised funds for social activities.
• Participated and qualified in math, science Olympiads and many inter school
competitions Won in quiz competitions and cultural activities at school and college
level.
PERSONAL PROFILE
Name : Ushasree Kotta
D.O.B : January 4, 1989
Husband’s Name : Suchetan Reddy K
Father’s Name : G. Satyanarayana Reddy
Mother’s Name : G. Mani
Permanent Address : H.no: 11-13-350/2, Road no 11, Alkapuri Colony, Hyd.
Languages : English, Hindi, Telugu
Hobbies : Social service, Reading books & playing chess