SPICE活用入門 (02AUG2013)

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SPICE活用入門 (02AUG2013)

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SPICE活用入門 (02AUG2013)

  1. 1. 1.SPICEの最適な環境について 2.SPICEの弱点について 3.SPICEの再現性を高める方法について 4.収束エラー改善方法について 5.質疑応答 SPICE活用入門 1Copyright (C) Bee Technologies Inc. 2013
  2. 2. 1.SPICEの最適な環境について 環境 ツール SPICEモデル シミュレーション技術 2Copyright (C) Bee Technologies Inc. 2013
  3. 3. 1.SPICEの最適な環境について ツール 3Copyright (C) Bee Technologies Inc. 2013
  4. 4. 1.SPICEの最適な環境について SPICEモデル (1)サプライヤ企業から提供してもらう (2)スパイスモデル配信サイト:スパイス・パークを利用する → http://www.spicepark.info (3)自分で作成する →デバイスモデリング教材の活用 →デバイスモデリングセミナーの活用 →部品モデル作成術(書籍の活用) (4)デバイスモデリングサービスを活用する →半導体部品、受動部品、バッテリー、 センサー、モーター、機構部品等 (5)パラメータベースのシンプルモデルを活用する →シンプルモデル 4Copyright (C) Bee Technologies Inc. 2013
  5. 5. 1.SPICEの最適な環境について SPICEモデル:スパイスモデル配信サイト:スパイス・パーク 5Copyright (C) Bee Technologies Inc. 2013
  6. 6. 1.SPICEの最適な環境について シミュレーション技術=回路モデリング (1)概念設計 概念設計段階の回路方式の検討のテンプレート →コンセプトキット 電子書籍(Kindle,PDF)+デザインキット(PSpice,LTspice) →Kindle版はAMAZONで発売中 →PDF版は、マルツエレックで発売中 (2)詳細設計 詳細設計段階の回路方式の検討のテンプレート →デザインキット お客様の回路図をシミュレーション化 →カスタム・デザインキット 6Copyright (C) Bee Technologies Inc. 2013
  7. 7. 2.SPICEの弱点について (1)破壊の概念がない(耐圧の概念がない) →ヒューズのシンプルモデルの活用 (2)DC電源 安全動作領域がない 大電流が流れる →DC電源のシンプルモデルの活用 CVCC電源のシンプルモデルの活用 U1 CVCCPS CC = 5A CV = 5V 1 2 U1 DC_POWER_SUPPLY VOUT = 80Vdc IMAX = 160Adc VMAX = 80Vdc POWER = 1600W 7Copyright (C) Bee Technologies Inc. 2013
  8. 8. 2.SPICEの弱点について ヒューズ The model accounts for: • Current Rating • Fuse Factor • Internal Resistance • Normal Melting I2t Enable the model to simulate fusing time (blow time) as a function of I2t. The model can be used for testing the blow time for the different current pattern. A one-shot switch, once fuse is opened it cannot be closed. Fig.1 Fusing Time vs. Fusing Current Characteristic 0.001 0.01 0.1 1 10 0.1 1 10 100 FusingTime(Sec.) Fusing Current (A) 8Copyright (C) Bee Technologies Inc. 2013
  9. 9. 2.SPICEの弱点について ヒューズ Irate = the current rating of fuse [A] FF = Fusing Factor, the ratio of the minimum fusing current (the current that fuse start to heat up) to Irate. (e.g. Irate =400mA and the minimum fusing current is 620mA then FF = 620m/400m = 1.55) Rint = internal resistance of fuse I2t = Normal Melting value [A2, seconds] • From the fuse specification, the model is characterized by setting parameters Irate, FF, Rint and I2t. Model Parameters: Fig.2 Fuse model with default parameters IRATE = 400m FF = 1.55 RINT = 650m I2T = 0.024 9Copyright (C) Bee Technologies Inc. 2013
  10. 10. 2.SPICEの弱点について ヒューズ 0.001 0.01 0.1 1 10 0.1 1 10 100 FusingTime(Sec.) Fusing Current (A) Fig.3 Shows the complete setting of fuse model parameters by using data from the datasheet of CCF1N0.4 provided by KOA Speer Electronics, Inc. the minimum fusing current is 620mA, FF = 20m/400m = 1.55 IRATE = 400m FF = 1.55 RINT = 650m I2T = 0.024 10Copyright (C) Bee Technologies Inc. 2013
  11. 11. 2.SPICEの弱点について ヒューズ • The simulation result shows the fusing times, tF, (the time that fuse blows) at the different fuse currents, IF . tF = 956.677usec. at IF = 5A tF = 5.9221msec. at IF = 2A tF = 23.7861msec. at IF = 1A Simulation Circuit *Analysis directives: .TRAN 0 1s 0 100u .STEP PARAM dc_current LIST 1, 2, 5 *Integration Method: trapezoidal Simulation Result 11Copyright (C) Bee Technologies Inc. 2013
  12. 12. 2.SPICEの弱点について ヒューズ 0.001 0.01 0.1 1 10 0.1 1 10 100 FusingTime(Sec.) Fusing Current Measurement Simulation Graph shows the comparison result between the simulation result vs. the measurement data. The fusing current error (average from 0.001-10 sec.) = 4.9% Comparison Graph 12Copyright (C) Bee Technologies Inc. 2013
  13. 13. 2.SPICEの弱点について ヒューズ • The simulation result shows the fusing times, tF, (the time that fuse blows) for the same peak current but different in current patterns(waveforms). tF = 59.984msec. for sine wave tF = 150.041msec. for triangle wave Simulation CircuitSimulation Result .TRAN 0 0.2s 0 100u *Integration Method: trapezoidal 13Copyright (C) Bee Technologies Inc. 2013
  14. 14. 2.SPICEの弱点について ヒューズ 0.001 0.01 0.1 1 10 0.1 1 10 100 FusingTime(Sec.) Fusing Current Measurement Simulation If the most accurate result is required, we could provide the specific model that optimized for each part number of fuse. The fusing current error (average from 0.001- 10 sec.) will reduce from 4.9% (simplified model) to 0.4% (specific fuse model) Model of fuse part number CCF10.4, all parameters and function are already set Error reduce to 0.4% Comparison Graph 14Copyright (C) Bee Technologies Inc. 2013
  15. 15. 2.SPICEの弱点について DC電源 • This DC Power Supply Simplified SPICE Behavioral Model is for users who require the model of a DC power supply as a part of their system. • The model focuses on the power supply’s behavior in their operation area, which user can input rated voltage, rated power, and maximum output current. Rated output voltage Rated output line (from Rated Power) Output Voltage [V] Output Current [A] Operation Area Maximum output current 15Copyright (C) Bee Technologies Inc. 2013
  16. 16. 2.SPICEの弱点について DC電源 POWER  Rated power – e.g. 400W, 800W, 1600W – Value = <POWER> VMAX  DC maximum output voltage – e.g. 80V, 320V, 650V – Value = <VMAX> IMAX  DC maximum output current – e.g. 40A, 80A, 160A – Value = <IMAX> VOUT  Output voltage – 0 ~ VMAX – Value = <VOUT> • From the DC power supply specification, the model is characterized by setting parameters POWER, VMAX, and IMAX, then input VOUT value (from 0 to VMAX). U1 DC_POWER_SUPPLY VOUT = 80Vdc IMAX = 160Adc VMAX = 80Vdc POWER = 1600W Model Parameters: 16Copyright (C) Bee Technologies Inc. 2013
  17. 17. 2.SPICEの弱点について DC電源 I(OUT) 0A 20A 40A 60A 80A 100A 120A 140A 160A 180A 200A V(OUT) 0V 20V 40V 60V 80V 100V (160.000,9.990) (20.000,79.991) (160.000,9.990) Rated output voltage Maximum output current Rated output line Rated operation range 17Copyright (C) Bee Technologies Inc. 2013
  18. 18. 2.SPICEの弱点について DC電源 *Analysis directives: .DC LIN I_ILOAD 0 200 10m .PROBE V(*) I(*) W(*) D(*) NOISE(*) DC Sweep: ILOAD 0-200A 0 OUT OUT ILOAD U1 DC_POWER_SUPPLY VOUT = 80Vdc IMAX = 160Adc VMAX = 80Vdc POWER = 1600W 18Copyright (C) Bee Technologies Inc. 2013
  19. 19. 2.SPICEの弱点について DC電源 Time 0s 10ms V(OUT) 0V 20V 40V 60V 80V 100V Parameter VOUT = 40V 60V 80V, and 100V V(OUT) is limited by the model parameter VMAX (80V) 19Copyright (C) Bee Technologies Inc. 2013
  20. 20. 2.SPICEの弱点について CVCC電源 U1 CVCCPS CC = 5A CV = 5V 1 2 CV and CC value set only CV: Constant Voltage [V] CC: Constant Current [A] Default Value: CV=5V: Constant Voltage [V] CC=5A: Constant Current [A] 20Copyright (C) Bee Technologies Inc. 2013
  21. 21. 2.SPICEの弱点について CVCC電源 I_ILoad 0A 1.0A 2.0A 3.0A 4.0A 5.0A V(H1:1,H1:2) 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V 7.0V 8.0V CV=6V CV=5V CV=4V CC=5A I_ILoad 0A 1.0A 3.0A 5.0A 7.0A V(H1:1,H1:2) 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V 7.0V 8.0V CC=4A CC=5A CC=6A CV (Constant Voltage) CC (Constant Current) CV=5V 21Copyright (C) Bee Technologies Inc. 2013
  22. 22. 2.SPICEの弱点について CVCC電源 [How to set] .MODEL MPOPS PMOS + LEVEL=3 L=1u W=1u TOX=100n + VTO=-0.7 KP={22.2222*CC} RD={(0.37*CV)/CC} + RDS=100MEG N=1MEG Load Regulation I_ILoad 0A 1.0A 2.0A 3.0A 4.0A 5.0A V(H1:1,H1:2) 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V I_ILoad 0A 1.0A 2.0A 3.0A 4.0A 5.0A V(H1:1,H1:2) 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V RD={(0.1*CV)/CC} RD={(0.37*CV)/CC} Symbol of the CV|CC Power Supply Model U1 CVCCPS CC = 5A CV = 5V 1 2 22Copyright (C) Bee Technologies Inc. 2013
  23. 23. 2.SPICEの弱点について CVCC電源 I_ILoad 0A 1.0A 2.0A 3.0A 4.0A 5.0A V(H1:1,H1:2) 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V [How to set] .MODEL MPOPS PMOS + LEVEL=3 L=1u W=1u TOX=100n + VTO=-0.7 KP={22.2222*CC} RD={(0.37*CV)/CC} + RDS=100MEG N=1MEG Load Regulation The parameter RD is deleted Symbol of the CV|CC Power Supply Model U1 CVCCPS CC = 5A CV = 5V 1 2 23Copyright (C) Bee Technologies Inc. 2013
  24. 24. Most electronic ballasts and switching power supplies use a bridge rectifier and a bulk storage capacitor to derive raw dc voltage from the utility ac line, figure above: Vin=100Vac, 50Hz and PO=200W. 24 Vin AC_IN1 PARAMETERS: f req = 50Hz Vin = 100Vac AC_IN2 Cbulk 2000uF 0 bulkDB1 DB2DB3 Diode DB4 Load 1.414Adc Iline Vbulk 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  25. 25. Time 160ms 164ms 168ms 172ms 176ms 180ms 184ms 188ms 192ms 196ms 200ms AVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin)))) 0 0.2 0.4 0.6 0.8 1.0 ABS( I(Vin) ) 0A 10A 20A ABS( V(AC_IN1,AC_IN2) ) V(bulk) 0V 100V 200V SEL>> The Uncorrected Power Factor rectifying circuit draws current from the ac line when the ac voltage exceeds the capacitor voltage (Vbulk). The current (Iline) is non-sinusoidal. This results in a poor power factor condition where the apparent input power is much higher than the real power, figure above, power factor ratios of 0.5 to 0.7 are common. 25 |VAC, in, 100V| (VPEAK, in=100*2=141.42V) and Vbulk |Iline| Power Factor Ratio = Pin, avg./(Vin, rms* Iin, rms) 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  26. 26. Vac, in C1 1uF C2 200u ILoad 0.5A L1 12 Diode D2 Q1 MOSFET R7 L2 1 2 0 0 Rectifiers PFC TB6819AFG Controller Circuit PARAMETERS: f req = 50Hz Vin = 100Vac The Power Factor Correction (PFC) circuit, as an off-line active preconverter, is designed to draw a sinusoidal current from the AC line that is in phase with input voltage. As a result, the power factor ratio is improved to be near to ideal (1). The TB6819AFG is a critical conduction mode (CRM) PFC controller IC. The description including equation and constants as a guide to understand its designing process is included in this document. 26 Iline VDC, OUT 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  27. 27. Time*10 100ms 104ms 108ms 112ms 116ms 120ms 124ms 128ms 132ms 136ms 140ms AVG(ABS(W(Vin))) / (RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin)))) 0 0.2 0.4 0.6 0.8 1.0 -I(Vin) -8.0A 0A 8.0A SEL>> 1 V(AC_IN1,AC_IN2) 2 V(VOUT) -160V 0V 160V 1 200V 400V 600V 2 >> The poor power factor load is corrected by keeping the ac line current sinusoidal and in phase with the line voltage. This results with power factor ratio is 0.85. 27 VAC, in, 100V and VDC, OUT, 400V Iline Power Factor Ratio = 0.85 *simulation result at tscale = 10 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  28. 28. Load 0.5A R12 39k C9 0.1uF Vin FREQ = {f req} VAMPL = {Vin*1.414} AC_IN1 R4 100 PARAMETERS: f req = 50 Vin = 100 C6 3300p AC_IN2 C1 1u 0 0 R9 3MEG R10 22k C5 10nF C8 47uF IC = 17.9 D5 DZ18V R11 360k R6 68k R8 100k MULT Rtf C3 0.47uF IC = 3.74 L1 {L} 12 PARAMETERS: L = 230u N = {1/9.6} N=N2/N1, L2=(N^2)*L1 VCC V1 R7 0.11 POUT V2 U1 TB6819AFG FB_IN COMP MULT ISZCD GND POUT VCC FB_IN IS ZCD C7 8p R3 10k C4 1uF VOUT R2 1.5MEG R1 9.53k C2 200uF IC = {2.51*1509.53/9.53} COMP L2 {N*N*L} 1 2 K K1 COUPLING = 1 K_Linear L1 = L1 L2 = L2 DB1 Diode D2 Diode D3 Diode D4 DB2DB3 Diode DB4 Q1 MOSFET R5 10 28 VAC, in=85-265VAC PO = 200W, VDC, OUT = 400VDC *Analysis directives: .TRAN 0 20ms 0 100n .OPTIONS ABSTOL= 100n .OPTIONS GMIN= 1.0E-8 .OPTIONS ITL1= 500 .OPTIONS ITL2= 200 .OPTIONS ITL4= 40 .OPTIONS RELTOL= 0.01 .OPTIONS VNTOL= 100u 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  29. 29. Time 18.00ms 18.25ms 18.50ms 18.75ms 19.00ms 19.25ms 19.50ms 19.75ms 20.00ms ID(Q1) -6A 0A 6A 12A V(Q1:d,Q1:s) 0V 200V 400V 600V I(D2) 8A 16A -2A SEL>> V(D2:2,D2:1) 0V 200V 400V 600V Switching Devices VPEAK and IPEAK at Steady State 29 D2 VKA, Peak ≈ 400V at steady state Total simulation time = 976.83 seconds D2 IF, Peak ≈ 12A at steady state Q1 VDS, Peak ≈ 400V at steady state Q1 ID, Peak ≈ 7.2A at steady state 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  30. 30. Load 0.5A R12 39k C9 0.1uF Vin FREQ = {f req*tscale} VAMPL = {Vin*1.414} AC_IN1 R4 100 PARAMETERS: f req = 50 Vin = 85 C6 3300p AC_IN2 C1 1u 0 0 R9 3MEG R10 22k C5 {10n/tscale} C8 47uF IC = 17.9 D5 DZ18V R11 360k R6 68k R8 100k MULT Rtf C3 {0.47u/tscale} L1 {L} 12 PARAMETERS: L = 230u N = {1/9.6} N=N2/N1, L2=(N^2)*L1 VCC V1 R7 0.11 POUT V2 U1 TB6819AFG FB_IN COMP MULT ISZCD GND POUT VCC FB_IN ISZCD C7 8p R3 10k C4 {1u/tscale} VOUT R2 1.5MEG R1 9.53k C2 {200u/tscale} PARAMETERS: tscale = 40 COMP L2 {N*N*L} 1 2 K K1 COUPLING = 1 K_Linear L1 = L1 L2 = L2 DB1 Diode D2 Diode D3 Diode D4 DB2DB3 Diode DB4 Q1 MOSFET R5 10 Switching Devices VPEAK and IPEAK at Start Up 30 Vin, min = 85Vac with frequency 50Hz, tscale = 40 Iload = 0.5A as PO=200W at VO=400V I(D2) Switching Diode, D2 *Analysis directives: .TRAN 0 10ms 0m 100n .OPTIONS ABSTOL= 100n .OPTIONS GMIN= 1.0E-8 .OPTIONS ITL1= 500 .OPTIONS ITL2= 200 .OPTIONS ITL4= 40 .OPTIONS RELTOL= 0.01 .OPTIONS VNTOL= 100u ID(Q1) Switching MOSFET, Q1 Rectifier Diode, DB1-4 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  31. 31. Time 476us 480us 484us 488us 492us 496us 500us 504us 508us 512us 516us V(V2) 0V 40V -I(L1) 0A 5A 10A V(V1) 0V 250V 500V V(Q1:g) 10V 20V SEL>> Time 0s 0.5ms 1.0ms 1.5ms 2.0ms V(VOUT) 392V 400V 31 The Simulation Waveform with the defaults models V(V1) I (L1) V(V2) V(VOUT) without high frequency ripple which is caused by ESR and ESL of the capacitor model. Gate charge characteristics is not include in the default model. Total simulation time = 132.41 seconds 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  32. 32. Load 0.5A R12 39k Q2 2SK2611 C9 0.1uF Vin FREQ = {f req*tscale} VAMPL = {Vin*1.414} AC_IN1 R4 100 PARAMETERS: f req = 50 Vin = 100 C6 3300p AC_IN2 C1 1u 0 0 R9 3MEG R10 22k C5 {10n/tscale} C8 47uF IC = 17.9 D5 DZ18V R11 360k R6 68k R8 100k MULT Rtf C3 {0.47u/tscale} IC = 3.74 L1 {L} 12 PARAMETERS: L = 230u N = {1/9.6} N=N2/N1, L2=(N^2)*L1 VCC V1 R7 0.11 POUT V2 U1 TB6819AFG FB_IN COMP MULT ISZCD GND POUT VCC FB_IN ISZCD C7 8p R3 10k C4 {1u/tscale} VOUT R2 1.5MEG R1 9.53k COMP L2 {N*N*L} 1 2 K K1 COUPLING = 1 K_Linear L1 = L1 L2 = L2 C2 RJJ-35V221MG5-T20 D2 SCS110AG DB1 Diode D3 Diode D4 PARAMETERS: tscale = 10 DB2DB3 Diode DB4 R5 10 Simulation with Models from the SpicePark 32 Capacitor model MOSFET professional model Schottky diode model Replace some default model with models from SpicePark *Analysis directives: .TRAN 0 2ms 0 100n .OPTIONS ABSTOL= 100n .OPTIONS GMIN= 1.0E-8 .OPTIONS ITL1= 500 .OPTIONS ITL2= 200 .OPTIONS ITL4= 100 .OPTIONS RELTOL= 0.01 .OPTIONS VNTOL= 100u 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  33. 33. 【参考】インダクタの等価回路の考え方 10 -3 10 0 10 3 10 6 10 9 (Hz) Impedance vs. Frequency Inductor model R1L1 L1 R1 R1L1 C1 L1 10 -3 10 0 10 3 10 6 10 9 (Hz) Impedance vs. Frequency Inductor model R1L1 R1L1 L1 R1 L1 R1 R1L1 C1 R1L1 C1 L1L1 33 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  34. 34. Frequency 1.0KHz 10KHz 100KHz 1.0MHz 10MHz V(V1:+)/ I(V1) 1.0 10 100 1.0K 10K 100K (2.1878M,234.735K) All Rights Reserved Copyright (C) Bee Technologies Inc. 34 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  35. 35. ラダー・モデル(Rudder Model) Frequency 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(N01685)/I(V2) 10m 100m 1.0 10 100 1.0K 10K 35 C1 1 2 R1 L2 C2 L1 R2 RS *$ *PART NUMBER: SF-T5-25-01-PF *MANUFACTURER: TDK *All Rights Reserved Copyright (c) Bee Technologies Inc. 2006 .SUBCKT SF-T5-25-01-PF 1 2 R1 1 N4 2.89441k RS N4 2 37.9262m C1 1 N4 5.81894p L1 1 N3 12.151u L2 N3 N4 24.0673u R2 N3 N4 592.966 C2 N3 N4 2.2969p .ENDS *$ SPICEシミュレーション結果 インピーダンス測定結果(Agilent 4294A) 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  36. 36. Time 484us 488us 492us 496us 500us 504us 508us 512us 516us 520us 524us V(V2) 0V 40V -I(L1) 0A 5A 10A V(V1) 0V 250V 500V V(Q2:g) 10V 20V SEL>> Time 0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms V(VOUT) 392V 400V 36 V(VOUT) with high frequency ripple which is caused by ESR and ESL of the capacitor model. Gate charge characteristics is include in the MOSFET Professional model. V(V1) I (L1) V(V2) Total simulation time = 408.13 seconds 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  37. 37. 37 パワーMOSFETのスパイスモデルについて MOSFET LEVEL LEVEL=1 Shichman-Hodges Model LEVEL=2 形状に基づいた解析モデル LEVEL=3 半経験則短チャネルモデル LEVEL=4 BSIM Model LEVEL=6 BSIM3 MODEL ・・・・・・・ ・・ MOSFET LEVEL=3 半経験則短チャネルモデルの特徴 (1)2次元的な電位分布によるデバイスの長さ及び幅に対してスレッシュホルド電圧 が敏感に影響を受ける。 (2)ドレインが誘起するBarrier loweringによるドレイン電圧に対してのスレッシュホルド電圧 の考慮。 (3)リニア領域と飽和領域との間での緩やかな変化及びホットエレクトロンの速度 飽和によって若干減少する飽和電圧、飽和電流の考慮。 RB BulkGate Cbs Cgb RG Cgd ROS Cgs RD RS Cbd Drain Source Idrain 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  38. 38. 38 Time*1ms 0 8n 16n 24n 32n 40n V(W1:2) V(W201:2) 0V 2V 4V 6V 8V 10V 12V 14V 16V 18V 20V MOSFET LEVEL=3 MODEL Bee Technologies MODEL(Professional) ゲートチャージ特性 ミラー容量が固定値のため、ミラー容量を可変にする 電流臨界モード方式PFC制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  39. 39. 39 Condition : Po = 25[W], 4 Load Analysis Time Domain (Transient) Run to time: 3ms Start saving data after: 1ms Maximum step size: 100n  Skip the initial transient bias point calculation (SKIPBP) .Options RELTOL: 0.01 VNTOL: 1.0u ABSTOL: 1.0n CHGTOL: 0.01p GMIN: 1.0E-12 ITL1: 500 ITL2: 200 ITL4: 10 TEST CONDITION: C4 1nF 0 +B 15V + C18 EKMG500ELL222MLP1S C5 1nF 0 R18 10 0 R19 2.2k PARAMETERS: Po = 25W Gv = 15.85 RL = 4 f in = 1kHz C14 MMH250K684 R4 220 C7 10u IC = 10 R2 3k R1 100k C10 22u IC = 15 LOAD {RL} OUT C9 22u IC = 12.85 MUR120RLG D2 IN VS R13 10 R3 47k L1 7G14N-220-RB VB R17 1 R20 3.3k 0 R21 8.2k R8 820 +B VAA 0 VREF R6 8.2k R7 1.2k CSD OCSET IN- IC1 IRS2092 VAA GND IN- COMP CSD VSS VREF OCSET DT COM LO VCC VS HO VB CSH VCC 0 DT VSS 0 COMP R5 820 -B HO R15 10 LO VR1 75 -B -15V 0 C2 10u IC = 7 C8 10u IC = 7 R11 10k V1 FREQ = {f in} VAMPL = {1.4142*SQRT(Po*RL)/Gv } VOFF = 0 VS CSH C13 MMC400K104 0 C12 MMC250K474 R16 10 C11 RPER11H104K2K1A01B C15 RPER11H104K2K1A01B 0 R14 4.7 MUR120RLG D1 0 R9 4.7k + C16 EKMG500ELL222MLP1S C17 RPER11H104K2K1A01B R12 10k C3 RPER11H103K2K1A01B + C1 EKMG500ELL100ME11D C6 AMZ0050J102 FET1 IRFIZ24N FET2 IRFIZ24N Ls1 20nH 1 2 Ls2 20nH 1 2 Ls3 20nH 1 2 Ls4 20nH 1 2 Ls5 20nH 12 D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  40. 40. 40 Time 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 1 AVG(W(LOAD)) -(AVG(W(+B))+AVG(W(-B))) 2 -100*AVG(W(LOAD))/(AVG(W(+B))+AVG(W(-B))) 0W 5W 10W 15W 20W 25W 30W 35W 40W 45W 50W 1 >> 0 10 20 30 40 50 60 70 80 90 100 2 PSUPPLY [W] PO [W] %Efficiency Specifications : Efficiency Simulation Result D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  41. 41. + - SPEAKER F120A FET1 IRFIZ24N FET2 IRFIZ24N + C1 EKMG500ELL100ME11D C6 AMZ0050J102C3 RPER11H103K2K1A01B V1 FREQ = {f in} VAMPL = { 1.4142*VOUT/Gv } VOFF = 0 0 C4 1nF +B 15V + C18 EKMG500ELL222MLP1S C5 1nF 0 R18 10 0 R19 2.2k C14 MMH250K684 R4 220 C7 10u IC = 10 R2 3k R1 100k C10 22u IC = 15 OUT C9 22u IC = 12.85 MUR120RLG D2 VS IN R13 10 R3 47k L1 7G14N-220-RB VB R17 1 0 R20 3.3k R21 8.2k R8 820 +B VREF VAA 0 R6 8.2k R7 1.2k CSD OCSET IN- IC1 IRS2092 VAA GND IN- COMP CSD VSS VREF OCSET DT COM LO VCC VS HO VB CSH VCC 0 DT VSS 0 COMP HO R5 820 -B R15 10 LO VR1 75 -B -15V 0 C2 10u IC = 7 C8 10u IC = 7 R11 10k CSH VS C13 MMC400K104 0 C12 MMC250K474 R16 10 C11 RPER11H104K2K1A01B C15 RPER11H104K2K1A01B 0Ls1 20nH 1 2 Ls2 20nH 1 2 Ls3 20nH 1 2 Ls4 20nH 1 2 R14 4.7 MUR120RLG D1 0 R9 4.7k + C16 EKMG500ELL222MLP1S Ls5 20nH 12 C17 RPER11H104K2K1A01B R12 10k PARAMETERS: VOUT = 2 Gv = 15.85 f in = 1k V V V V V V 41 Time 505.0us 510.0us V(VS) -40V 0V 40V Time 505.0us 510.0us V(HO) -40V 0V 40V Time 505us 510us503us 513us V(LO) -20V 0V Time 0.50ms 0.75ms 1.00ms 1.25ms V(IN) 0V -200mV 200mV Time 505.0us 510.0us V(COMP) 0V -1.0V 1.0V Class D amplifier circuit are simulated and compared with measured waveforms from oscilloscope (Tektronix: TDS3054B) Time 0s 0.3ms 0.7ms V(OUT) -4.0V 0V 4.0V D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  42. 42. 42 Time 1.988ms 1.990ms 1.992ms 1.994ms 1.996ms 1.998ms V(VS) -40V -30V -20V -10V 0V 10V 20V 30V 40V OUT VS Simulated Measured D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  43. 43. 43 Time 1.988ms 1.990ms 1.992ms 1.994ms 1.996ms 1.998ms V(HO) -40V -30V -20V -10V 0V 10V 20V 30V 40V Time 1.992ms 1.994ms 1.996ms 1.998ms 2.000ms 2.002ms V(LO) -40V -30V -20V -10V 0V 10V 20V 30V 40V HO LO Simulated Measured D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  44. 44. 44 Self-oscillation frequency = 400kHz (Simulated) Self-oscillation frequency = 400kHz (Measured) Simulated Measured OUT OUT VS VS Self-Oscillating Frequency D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  45. 45. + - SPEAKER F120A FET1 IRFIZ24N FET2 IRFIZ24N + C1 EKMG500ELL100ME11D C6 AMZ0050J102C3 RPER11H103K2K1A01B V1 FREQ = 1k VAMPL = 0 VOFF = 0 0 C4 1nF +B 15V + C18 EKMG500ELL222MLP1S C5 1nF 0 R18 10 0 R19 2.2k C14 MMH250K684 R4 220 C7 10u IC = 10 R2 3k R1 100k C10 22u IC = 15 OUT C9 22u IC = 12.85 MUR120RLG D2 VS IN R13 10 R3 47k L1 7G14N-220-RB VB R17 1 0 R21 8.2k R20 3.3k R8 820 +B VREF VAA 0 R6 8.2k R7 1.2k CSD OCSET IN- IC1 IRS2092 VAA GND IN- COMP CSD VSS VREF OCSET DT COM LO VCC VS HO VB CSH VCC 0 DT VSS 0 COMP HO R5 820 -B R15 10 LO VR1 75 -B -15V 0 C2 10u IC = 7 C8 10u IC = 7 R11 10k CSH VS C13 MMC400K104 0 C12 MMC250K474 R16 10 C11 RPER11H104K2K1A01B C15 RPER11H104K2K1A01B 0Ls1 20nH 1 2 Ls2 20nH 1 2 Ls3 20nH 1 2 Ls4 20nH 1 2 R14 4.7 MUR120RLG D1 0 R9 4.7k + C16 EKMG500ELL222MLP1S Ls5 20nH 12 C17 RPER11H104K2K1A01B R12 10k Dead-time 45 Dead-time Mode R20 R21 DT1 (25ns) 3.3k 8.2k DT2 (40ns) 5.6k 4.7k DT3 (65ns) 8.2k 3.3k DT4 (105ns) - < 10k V(DT) Voltage Divider Analysis Time Domain (Transient) Run to time: 1ms Start saving data after: 0.5m Maximum step size: 40n  Skip the initial transient bias point calculation (SKIPBP) .Options RELTOL: 0.001 VNTOL: 1.0u ABSTOL: 1.0n CHGTOL: 0.01p GMIN: 1.0E-12 ITL1: 500 ITL2: 200 ITL4: 10 D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  46. 46. Dead-time DT1(25ns) 46 Time 0.9976ms 0.9980ms 0.9984ms 0.9988ms 0.9992ms0.9974ms V(LO,-B) V(HO,VS) -4V 0V 4V 8V 12V 16V V(OUT) 0V -400mV 400mV SEL>> DT1(25ns) DT1(25ns) Spike voltage D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  47. 47. Dead-time DT3(65ns) 47 Time 0.9976ms 0.9980ms 0.9984ms 0.9988ms 0.9992ms 0.9996ms V(LO,-B) V(HO,VS) -4V 0V 4V 8V 12V 16V V(OUT) 0V -400mV 400mV SEL>> DT3(65ns) DT3(65ns) Spike voltages (Decrease for longer dead time) D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  48. 48. + C1 EKMG500ELL100ME11D C6 AMZ0050J102C3 RPER11H103K2K1A01B C17 RPER11H104K2K1A01B + C18 EKMG500ELL222MLP1S FET1 IRFIZ24N FET2 IRFIZ24N + - SPEAKER F120A 0 C4 1nF +B 15V C5 1nF 0 R18 10 0 R19 2.2k C14 MMH250K684 R4 220 C7 10u IC = 10 R2 3k R1 100k C10 22u IC = 15 OUT C9 22u IC = 12.85 MUR120RLG D2 VS IN R13 10 R3 47k L1 7G14N-220-RB VB R17 1 0 R20 3.3k R21 8.2k R8 820 +B VREF VAA 0 R6 8.2k R7 1.2k CSD OCSET IN- IC1 IRS2092 VAA GND IN- COMP CSD VSS VREF OCSET DT COM LO VCC VS HO VB CSH V1 FREQ = 1k VAMPL = 0 VOFF = 0 VCC 0 DT VSS 0 COMP HO R5 820 -B R15 10 LO VR1 75 -B -15V 0 C2 10u IC = 7 C8 10u IC = 7 R11 10k CSH VS C13 MMC400K104 0 C12 MMC250K474 R16 10 C11 RPER11H104K2K1A01B C15 RPER11H104K2K1A01B 0Ls1 20nH 1 2 Ls2 20nH 1 2 Ls3 20nH 1 2 Ls4 20nH 1 2 R14 4.7 MUR120RLG D1 0 R9 4.7k + C16 EKMG500ELL222MLP1S Ls5 20nH 12 R12 10k The total power loss in MOSFET are given by: PTOTAL = PSW+Pcond+Pgd 48 Power losses in the MOSFETs Analysis Time Domain (Transient) Run to time: 500us Start saving data after: 100n Maximum step size: 2n  Skip the initial transient bias point calculation (SKIPBP) .Options RELTOL: 0.003 VNTOL: 1.0m ABSTOL: 100n CHGTOL: 0.01p GMIN: 1.0E-12 ITL1: 500 ITL2: 200 ITL4: 20 D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  49. 49. Time 23.6us 24.4us 25.2us 26.0us 26.8us 27.6us 1 V(FET1:S,FET1:D) 2 -I(Ls1) 3 V(FET1:D,FET1:S)*-I(Ls1) 0V 100V -60V 1 -1.5A -1.0A -0.5A 0A 0.5A 1.0A 1.5A 2.0A 2.5A 2 >> -50W 0W 20W 3 Power losses FET1(Professional Model) 49 FET1: ID and VDS are simulated and compared with scope (Tektronix: TDS3054B) waveforms PSW ,Pcond ,and Pgd are calculated by PSpice. VDS, ID (Measured) -VDS ID -VDS ID Power loss (VDS*ID) PSWPgd Pcond VDS, ID (Simulated) D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  50. 50. Time 492.8us 493.6us 494.4us 495.2us 496.0us 1 V(FET2:D,FET2:S) 2 -I(Ls3:1) 3 V(FET2:D,FET2:S)*-I(Ls3:1) 0V 100V -40V 1 -1.0A -0.5A 0A 0.5A 1.0A 1.5A 2.0A 2.5A 3.0A 2 >> -50W 0W 20W 3 Power losses FET2(Professional Model) 50 FET2: ID and VDS are simulated and compared with scope (Tektronix: TDS3054B) waveforms PSW ,Pcond ,and Pgd are calculated by PSpice. VDS ID VDS ID Power loss (VDS*ID) PSWPgd Pcond VDS, ID (Measured)VDS, ID (Simulated) 3.2 D級アンプ Copyright (C) Bee Technologies Inc. 2013
  51. 51. • Gate charge characteristics in Professional model has more accurate results than standard model. FET: IRFIZ24N Qg Standard vs. Professional Model 51 IRFIZ24N (Standard) IRFIZ24N (Professional) VDD=44V,ID=10A ,VGS=10V Measurement Simulation Error (%) Standard Model: Qg(nc) 13.400 12.543 -6.396 Professional Model: Qg(nc) 13.400 13.409 0.067 3.2 D級アンプ Copyright (C) Bee Technologies Inc. 2013
  52. 52. Time 867us 869us 871us 873us 875us 877us 1 V(OUT) 2 V(VS) -1.0V -0.5V 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 1 >> -120V -80V -40V 0V 40V 2 52 Simulated (without output capacitor models) Measured OUT OUT VS VS Self-oscillation frequency = 400kHz (Simulated) Self-oscillation frequency = 400kHz (Measured) Simulation Result (without Capacitor Model) 3.2 D級アンプ Copyright (C) Bee Technologies Inc. 2013
  53. 53. 53 Simulated (with output capacitor models) Measured OUT OUT VS VS Self-oscillation frequency = 400kHz (Simulated) Self-oscillation frequency = 400kHz (Measured) Simulation Result (with Capacitor Model) D級アンプ 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  54. 54. Application Circuit 54 O_A O_A1 O_B1 O_B O_B RRSA 0.5ohm O_B1 V5 Vref AB 1.25Vdc O_A1 O_A RSB L2 IC = 0 1 2 0 Cv ref AB 1uF 00 L1 IC = 0 12 RSA RRSB 0.5ohm 0 VM1 24V CVM1 100uF 00 U1 TB62206FG CCP1 = 0.22UF CCP2 = 0.01UF VM = 24 COSC = 560PF ROSC = 3.6K FIN CR VDD VREF_A VREF_B RS_B RS_A VM CCP_C CCP_B CCP_A STANDBY OUT_A1 PHASE_A PHASE_B OUT_A OUT_B ENABLE_A ENABLE_B OUT_B1 TORQUE V_PHASE_A TD = 0 TF = {tf phase} PW = {pwphase} PER = {tphase} V1 = 0 TR = {trphase} V2 = 5V V_PHASE_B TD = {tphase/4} TF = {tf phase} PW = {pwphase} PER = {tphase} V1 = 0V TR = {trphase} V2 = 5 0 0 PARAMETERS: f phase = 250Hz tphase = {1/f phase} tdphase = {trphase+pwphase/2} pwphase = {-2*trphase+tphase/2} trphase = 100n tf phase = {trphase} VDD 5Vdc C1 10uF 0 0 Rosc 3.6kohm 0 Cosc 560pF 0 Cccp_1 0.22uF Cccp_2 0.022uF 250Hz Full Step Ph_B Ph_A Ph_B Ph_A ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  55. 55. O_B1 O_B O_A O_A1 RSB 7.9ohm L2 9.15mH IC = -0.5 1 2 L1 9.15mH IC = -0.5 12 RSA 7.9ohm O_A O_A1 O_B1 O_B RRSA 0.5ohm V5 Vref AB 1.25Vdc 0 Cv ref AB 1uF 00 RRSB 0.5ohm 0 VM1 24V CVM1 100uF 00 U1 TB62206FG CCP1 = 0.22UF CCP2 = 0.01UF VM = 24 COSC = 560PF ROSC = 3.6K FIN CR VDD VREF_A VREF_B RS_B RS_A VM CCP_C CCP_B CCP_A STANDBY OUT_A1 PHASE_A PHASE_B OUT_A OUT_B ENABLE_A ENABLE_B OUT_B1 TORQUE V_PHASE_A TD = {tphase/4} TF = {tf phase} PW = {pwphase} PER = {tphase} V1 = 0 TR = {trphase} V2 = 5V V_PHASE_B TD = {tphase/2} TF = {tf phase} PW = {pwphase} PER = {tphase} V1 = 0V TR = {trphase} V2 = 5 0 0 PARAMETERS: f phase = 250Hz tphase = {1/f phase} tdphase = {trphase+pwphase/2} pwphase = {-2*trphase+tphase/2} trphase = 100n tf phase = {trphase} VDD 5Vdc C1 10uF 0 0 Rosc 3.6kohm Cosc 560pF 0 0 Cccp_1 0.22uF Cccp_2 0.022uF 250Hz Full Step Ph_B Ph_A Ph_B Ph_A Full Step Switching Sequence 55 Full-step sequences control signals Analysis Time Domain (Transient) Run to time: 8ms Start saving data after: 0ms Maximum step size: - .Options RELTOL: 0.01 VNTOL: 1.0m ABSTOL: 1.0n CHGTOL: 1p GMIN: 1.0E-12 ITL1: 500 ITL2: 200 ITL4: 100 ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  56. 56. Full Step Switching Sequence 56 • This figure shows the simulation result of the circuit with Full- step switching sequence. Phase A Phase B Enable A Enable B IOUT A IOUT B Time 0s 4.0ms 8.0ms I(U1:OUT_B1) -1.0A 0A 1.0A I(U1:OUT_A1) -1.0A 0A 1.0A V(U1:ENABLE_B) 0V SEL>> V(U1:ENABLE_A) 0V V(PH_B) 0V V(PH_A) 0V ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  57. 57. Time 2.54ms 2.58ms I(U1:OUT_B1) 400mA 600mA I(U1:OUT_A1) 400mA 600mA SEL>> Output Ripple Current • This figure shows the output ripple current of the Mixed Decay Mode ,which consist of Charge ,Slow decay ,and Fast decay mode ,with 101kHz chopping frequency. 57 IOUT = 0.5A fchop = 101kHz IOUT A IOUT B Charge mode Slow decay mode Fast decay mode ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  58. 58. Time 2.593ms 2.595ms 2.597ms 2.599ms 2.601ms 2.603ms I(U1:OUT_A1) 300mA 400mA 500mA 600mA 700mA SEL>> Ripple Current Simulation • The simulation result shows the current ripple that agrees to the measurement data. 58 Current ripple Current ripple Simulation Measurement ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  59. 59. Parameter Settings If there is no measurement data, the default value will be used: Rm: motor winding resistance [] Lm: motor winding inductance [H] Data is given by D.C. motor spec-sheet: V_norm: normal voltage [V] mNm: normal load [mNm] kRPM_norm: speed at normal load [kr/min] I_norm: current at normal load [A] Load Condition: IL: load current [A] 59 Model Parameters: D.C. Motor model and Parameters with Default Value - + U1 SMPL_DC_MOTOR Rm = 0.1 Lm = 100u I_norm = 6.1 mNm = 19.6 V_norm = 7.2 kRPM_norm = 14.4 IL = 6.1 ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  60. 60. 60 Time 0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms 360ms 400ms I(VIM) 0A 10A 20A V(VM) 0V 5V 10V SEL>> I(X_U1.V_kRPM) 0A 10A 20A V(X_U1.TRQ) 0V 40V 80V D.C. Motor Current = 6.1A D.C. Motor Voltage = 7.2V D.C. Motor Speed = 14.4krpm Torque Load= 19.6mNm ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  61. 61. Time 0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms 360ms 400ms I(VIM) 0A 10A 20A V(VM) 0V 5V 10V I(X_U1.V_kRPM) 0A 10A 20A SEL>> V(X_U1.TRQ) 0V 40V 80V 61 D.C. Motor Current = 3.05A D.C. Motor Voltage = 8.725V D.C. Motor Speed = 18.4krpm Torque Load= 9.8mNm ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  62. 62. - + U2 SMPL_DC_MOTOR Rm = 0.576 Lm = 165u I_norm = 2.9 mNm = 9.8 V_norm = 7.2 kRPM_norm = 14.2 IL = 0.6 NC NC NCA K VCC VO GND U1 TLP350 V1 TD = 0 TF = 10n PW = 199.99u PER = 400u V1 = 0 TR = 10n V2 = 1.8 0 R1 1u 0 Vcc 15V 0 VCC VDD 0 RG 120 0 DGT10J321_s D3 VCC Vdd 15V VDD 0 D4001 D2 U3 GT10J321 62 Simplified D.C. Motor with RS- 380PH Spec at No load. Simulation Circuit and Setting No load IL=0.6 Application Example ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  63. 63. Time -100ms 0s 100ms 300ms 500ms 700ms 900ms 1 I(U2:1) 2 V(U2:1,U2:2) -2A 0A 2A 4A 6A 8A 10A 12A 14A 1 -60V -50V -40V -30V -20V -10V 0V 10V 20V 2 >> Application Example 63 Measurement Simulation Motor Current (2A/Div) Motor Voltage (10V/Div) ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  64. 64. Time 898.0ms 898.4ms 898.8ms 899.2ms 899.6ms 1 I(U3:C) 2 V(U3:C) 3 V(U3:G) -2A 0A 2A 4A 6A 8A 10A 12A 14A 1 >> -30V -20V -10V 0V 10V 20V 30V 40V 50V 2 -60V -50V -40V -30V -20V -10V 0V 10V 20V 3 Application Example 64 Measurement Simulation IGBT: VGE IGBT: VCE IGBT: IC IGBT: VGE (10V/Div) IGBT: VCE (10V/Div) IGBT: IC (2A/Div) ステッピングモータ制御回路 3.SPICEの再現性を高める方法 Copyright (C) Bee Technologies Inc. 2013
  65. 65. 4. 収束エラー改善方法について 65Copyright (C) Bee Technologies Inc. 2013 (1)解析の刻みを変更する →刻みを荒くする (2).OPTIONSで改善する →それぞれのパラメータで改善する (3)回路で改善する →スナバ回路等を追加する
  66. 66. 4. 収束エラー改善方法について 66Copyright (C) Bee Technologies Inc. 2013
  67. 67. 4. 収束エラー改善方法について 67Copyright (C) Bee Technologies Inc. 2013
  68. 68. 4. 収束エラー改善方法について 68Copyright (C) Bee Technologies Inc. 2013 パラメータ 単位 説明 RELTOL 電圧及び電流の相対精度 VNTOL V 電圧の最高精度 ABSTOL A 電流の最高精度 CHGTOL Q 電荷の最高精度 GMIN 1/Ω 全ての分岐の最小コンダクタンス ITL1 DC、バイパスの繰り返し上限(予測なし) ITL2 DC、バイパスの繰り返し上限(予測あり) ITL4 過渡の時間ポイントの繰り返し制限
  69. 69. 4. 収束エラー改善方法について 69Copyright (C) Bee Technologies Inc. 2013 パラメータ 対処 ITL1 バイパスポイントを解析中に収束エラー発生時に対処 ITL2 DC解析中に収束エラー発生時に対処 ITL4 過渡解析中に収束エラー発生時に対処 ITLの対処方法 パワーエレクトロニクス分野の解析の場合 パラメータ 対処 VNTOL 大電圧の場合に対処 ABSTOL 大電流の場合に対処
  70. 70. 4. 収束エラー改善方法について 70Copyright (C) Bee Technologies Inc. 2013 Standard Default .OPTIONS RELTOL=0.001 VNTOL=1.0u ABSTOL=1.0p CHGTOL=0.01p GMIN=1.0E-12 ITL1=150 ITL2=20 ITL4=10 Simulation Convergence Quick Fix .OPTIONS RELTOL=0.01 VNTOL=1.0m ABSTOL=1.0n CHGTOL=0.01u GMIN=1.0E-12 ITL1=500 ITL2=200 ITL4=100
  71. 71. 71Copyright (C) Bee Technologies Inc. 2013 質疑・応答

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