1.
<PLAINTEXT>
########################################################################
#
# Ethernet Testing Program: This program sets up GPU sbc and prepares
# it to transmit and receive packets. It then transmits while
# polling for receives. When a receive occurs, it is buffered
# back to DRAM in continuous list of buffers for external scrutiny.
#
########################################################################
.globl start
#FPGA dram related registers
reg_ad_h .equ 0x4000
dram_ad_0 .equ 0x018c
dram_da_h0 .equ 0xffff
dram_da_l0 .equ 0xfffe
dram_ad_1 .equ 0x018c
dram_da_h1 .equ 0xffff
dram_da_l1 .equ 0xfffd
dram_ad_2 .equ 0x01c8
dram_da_2 .equ 0x0032
dram_ad_3 .equ 0x0008
dram_da_h3 .equ 0xf4ff
dram_da_l3 .equ 0x8fbf
dram_ad_4 .equ 0x0144

2.
dram_da_4 .equ 0x1000
dram_ad_5 .equ 0x0148
dram_da_5 .equ 0x0186
dram_ad_6 .equ 0x01cc
dram_da_6 .equ 0x170c
dram_ad_7 .equ 0x01c0
dram_da_h7 .equ 0xffff
dram_da_l7 .equ 0x17ff
dram_ad_8 .equ 0x016c
dram_da_8 .equ 0x0000
# Memory management values
#double up all _u values(so I don't try to load a 0x8000)
bat_0_u_u .equ 0x607C
bat_0_u_l .equ 0x0000
bat_0_l_u .equ 0x4000
bat_0_l_l .equ 0x0000
bat_1_l_u .equ 0x5200
bat_1_l_l .equ 0x4000
bat_1_u_u .equ 0x603C
bat_1_u_l .equ 0x4000
#Ethernet related registers
fpga_base .equ 0x4000
sram_base .equ 0x4004

3.
fpga_et_ad .equ 0x0078
fpga_et_op .equ 0x007C
fpga_et_rd .equ 0x0008
ether_cmd .equ 0x0000
ether_tx_now .equ 0x0026
ether_reset .equ 0x0021
ether_pg_0 .equ 0x0022
ether_pg_1 .equ 0x0062
ether_pg_2 .equ 0x00a2
ether_pstart .equ 0x0001
ether_pstop .equ 0x0002
ether_boundry .equ 0x0003
ether_txpstrt .equ 0x0004
ether_txbytel .equ 0x0005
ether_txbyteh .equ 0x0006
ether_isr .equ 0x0007
ether_rcr .equ 0x000c
ether_tcr .equ 0x000d
ether_dcr .equ 0x000e
ether_imr .equ 0x000f
ether_adr_0 .equ 0x00cb
ether_adr_1 .equ 0x0044
ether_adr_2 .equ 0x008c
ether_adr_3 .equ 0x00c0
ether_adr_4 .equ 0x0000

4.
ether_adr_5 .equ 0x0000
.text
start:
bl init_regs
bl init_mmu
bl init_ram
bl init_sram
bl init_ether
while_loop:
bl transmit
bl delay_loop
bl while_loop
init_regs:
li r0,0x0000
li r1,0x0000
li r2,0x0000
li r3,0x0000
li r4,0x0000
li r5,0x0000
li r6,0x0000
li r7,0x0000

5.
li r8,0x0000
li r9,0x0000
li r10,0x0000
li r11,0x0000
li r12,0x0000
li r13,0x0000
li r14,0x0000
li r15,0x0000
lis r24,0x646f
addi r24,r24,0x6e65
blr
init_mmu:
mfspr r4,1008
li r5,0x7fff
addi r5,r5,0x0001
or r4,r5,r4
mtspr 1008,r4
mfmsr r4
li r5,0x2010
or r4,r5,r4
mtmsr r4

6.
lis r4,bat_0_u_u
add r4,r4,r4
addi r4,r4,bat_0_u_l
mtspr 536,r4
#
lis r4,bat_0_l_u
add r4,r4,r4
addi r4,r4,bat_0_l_l
mtspr 537,r4
#
lis r4,bat_1_u_u
add r4,r4,r4
addi r4,r4,bat_1_u_l
mtspr 538,r4
#
lis r4,bat_1_l_u
add r4,r4,r4
addi r4,r4,bat_1_l_l
mtspr 539,r4
mfspr r4,1008
li r5,0x4000
or r4,r5,r4
mtspr 1008,r4

7.
lis r25,0x646f
addi r25,r25,0x6e65
blr
init_ram:
lis r4,reg_ad_h
addi r4,r4,dram_ad_0
lis r5,dram_da_h0
addi r5,r5,dram_da_l0
stw r5,0x0(r4)
li r5,0x7fff
li r4,0x0000
loop_d0:
addi r4,r4,0x0001
cmpw r4,r5
bnea loop_d0
addi r4,r4,dram_ad_1
lis r5,dram_da_h1
addi r5,r5,dram_da_l1
stw r5,0x0(r4)

8.
li r5,0x7fff
li r4,0x0000
loop_d1:
addi r4,r4,0x0001
cmpw r4,r5
bnea loop_d1
addi r4,r4,dram_ad_1
lis r5,dram_da_h1
addi r5,r5,dram_da_l1
stw r5,0x0(r4)
li r5,0x7fff
li r4,0x0000
loop_d2:
addi r4,r4,0x0001
cmpw r4,r5
bnea loop_d2
addi r4,r4,dram_ad_2
li r5,dram_da_2
stw r5,0x0(r4)
li r5,0x7fff
li r4,0x0000

9.
loop_d3:
addi r4,r4,0x0001
cmpw r4,r5
bnea loop_d3
lis r4,reg_ad_h
addi r4,r4,dram_ad_3
lis r5,dram_da_h3
addi r5,r5,dram_da_l3
stw r5,0x0(r4)
li r5,0x7fff
li r4,0x0000
loop_d4:
addi r4,r4,0x0001
cmpw r4,r5
bnea loop_d4
lis r4,reg_ad_h
addi r4,r4,dram_ad_4
li r5,dram_da_4
stw r5,0x0(r4)
lis r4,reg_ad_h
addi r4,r4,dram_ad_5
li r5,dram_da_5

10.
stw r5,0x0(r4)
lis r4,reg_ad_h
addi r4,r4,dram_ad_6
li r5,dram_da_6
stw r5,0x0(r4)
lis r4,reg_ad_h
addi r4,r4,dram_ad_7
lis r5,dram_da_h7
addi r5,r5,dram_da_l7
stw r5,0x0(r4)
lis r4,reg_ad_h
addi r4,r4,dram_ad_8
li r5,dram_da_8
stw r5,0x0(r4)
lis r26,0x646f
addi r26,r26,0x6e65
blr
init_sram:
li r4,0xa00 # Load the data address
lis r6,0x4004 # Load the sram address base upper
addi r6,r6,0x07fff # Load the sram address base lower
addi r6,r6,0x0001 # Load the sram address base lower

11.
lis r7,0x646f # Load in the packet end string
addi r7,r7,0x6e65 # ""
loop_0:
lwz r5,0x0(r4)
lfd f5,0x0(r4) # use pointer to load data
stfd f5,0x0(r6) # Store loaded word to sram
addi r4,r4,0x8 #
addi r6,r6,0x8 #
cmpw r5,r7 #
bne loop_0 #
lis r27,0x646f
addi r27,r27,0x6e65
blr
init_ether:
lis r1,fpga_base
lis r2,fpga_base
lis r3,fpga_base
addi r1,r1,fpga_et_ad
addi r2,r2,fpga_et_op
addi r3,r3,fpga_et_rd
li r10,0x0100 # r10 always holds ptr to next packet
li r15,0x0400

12.
li r17,0x0
li r4,ether_cmd
stw r4,0x0(r1)
li r4,ether_reset
stw r4,0x0(r2)
li r4,ether_pstart
stw r4,0x0(r1)
li r4,0x0001
stw r4,0x0(r2)
li r4,ether_pstop
stw r4,0x0(r1)
li r4,0x007f
stw r4,0x0(r2)
li r4,ether_boundry
stw r4,0x0(r1)
li r4,0x0001
stw r4,0x0(r2)
li r4,ether_txpstrt
stw r4,0x0(r1)
li r4,0x0080

13.
stw r4,0x0(r2)
li r4,ether_isr
stw r4,0x0(r1)
li r4,0x00ff
stw r4,0x0(r2)
li r4,ether_rcr
stw r4,0x0(r1)
li r4,0x001f
stw r4,0x0(r2)
li r4,ether_tcr
stw r4,0x0(r1)
li r4,0x0000
stw r4,0x0(r2)
li r4,ether_dcr
stw r4,0x0(r1)
li r4,0x004b
stw r4,0x0(r2)
li r4,ether_cmd
stw r4,0x0(r1)
li r4,ether_pg_1

14.
stw r4,0x0(r2)
li r4,0x1
stw r4,0x0(r1)
li r4,ether_adr_0
stw r4,0x0(r2)
li r4,0x2
stw r4,0x0(r1)
li r4,ether_adr_1
stw r4,0x0(r2)
li r4,0x3
stw r4,0x0(r1)
li r4,ether_adr_2
stw r4,0x0(r2)
li r4,0x4
stw r4,0x0(r1)
li r4,ether_adr_3
stw r4,0x0(r2)
li r4,0x5
stw r4,0x0(r1)
li r4,ether_adr_4

15.
stw r4,0x0(r2)
li r4,0x6
stw r4,0x0(r1)
li r4,ether_adr_5
stw r4,0x0(r2)
li r4,ether_cmd
stw r4,0x0(r1)
li r4,ether_pg_0
stw r4,0x0(r2)
lis r28,0x646f
addi r28,r28,0x6e65
blr
# Code to transmit generic data from data in sram(40048000)
transmit:
li r4,0x0a10 # Load the data address
addi r17,r17,0x0001
stw r17,0x0,(r4)
#
li r4,0x0a00 # Load the data address
li r5,0x0a40 # Load in dram data limit

16.
lis r6,0x4004 # Load the sram address base upper
addi r6,r6,0x07ff # Load the sram address base lower
addi r6,r6,0x0001 # Load the sram address base lower
#
loop_3:
lfd f5,0x0(r4) # use pointer to load data
stfd f5,0x0(r6) # Store loaded word to sram
addi r4,r4,0x8 #
addi r6,r6,0x8 #
cmpw r4,r5 #
bne loop_3 #
li r4,ether_cmd
stw r4,0x0(r1)
li r4,ether_pg_0
stw r4,0x0(r2)
li r4,ether_txpstrt
stw r4,0x0(r1)
li r4,0x0080
stw r4,0x0(r2)
li r4,ether_txbytel
stw r4,0x0(r1)
li r4,0x0040

17.
stw r4,0x0(r2)
li r4,ether_txbyteh
stw r4,0x0(r1)
li r4,0x0000
stw r4,0x0(r2)
li r4,ether_cmd
stw r4,0x0(r1)
li r4,ether_tx_now
stw r4,0x0(r2)
blr
# Loop to waste time while checking for receptions.
# If a reception is detected it is dma'ed and the chip setup up for
# more receptions. The delay/check loop then continues.
delay_loop:
li r9,0x7fff
li r8,0x0000
loop_1:
addi r8,r8,0x0001
cmpw r8,r9
bnea check_rx

18.
blr
check_rx:
li r4,ether_isr
stw r4,0x0(r1)
lwz r4,0x0(r2)
lwz r6,0x0(r3)
li r5,0x0001
and r4,r5,r6
cmpw r5,r4
bnea loop_1
prep_rx_dma:
# Reset the rx interrupt
li r4,ether_isr
stw r4,0x0(r1)
li r4,0x0001
stw r4,0x0(r2)
# Update sram rx dma ptr's to current buffer
lis r11,sram_base
lis r12,sram_base
add r11,r11,r10
add r12,r12,r10
lfd f4,0x0(r11)

19.
lfd f4,0x0(r11)
stfd f4,0x0b00(r0)
# Load next buffer ptr and update rx_bdry
li r4,ether_boundry
stw r4,0x0(r1)
lbz r10,0x0b00(r0)
stw r10,0x0(r2)
li r5,0x0008
slw r10,r10,r5
# Load byte count
lbz r4,0x0b03(r0)
slw r4,r4,r5
lbz r6,0x0b02(r0)
add r4,r6,r4
# Get the limit of this buffer read(buf addr + byte count)
add r12,r12,r4
addi r12,r12,0xf # Round up to get all data
lis r13,0xffff
li r13,0xfff8
and r12,r12,r13 # Ditch non 8 byte boundary bits
# Establish the Rx Dram buffer location( 1k to 7k)

20.
addi r15,r15,0x0600 # Increment the rx dram buffer ptr
li r16,0x7000
cmpw r15,r16
beq start_rx_dma
li r15,0x1000
start_rx_dma:
stw r15,0x0b08(r0)
lwz r16,0x0b08(r0)
loop_2:
lfd f4,0x0(r11) # Acquire word from sram
lfd f4,0x0(r11) # Ditto
stfd f4,0x0(r16) # Store loaded word to dram
addi r16,r16,0x8 #
addi r11,r11,0x8 #
cmpw r11,r12 #
bne loop_2 #
b loop_1
#blr # Will be replaced with loop_1 in operational
prog.
end: