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09.50 dhr van der zon


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09.50 dhr van der zon

  1. 1. Ben van der Zon BlueBird Back-end electonics assembly and packaging Acive Positionning “ Less is Better”
  2. 2. Background High Density Integration of semiconductor systems ambient intelligence Autonomous smart systems: more functionality per mm cube Improved performance More than Moore: Beyond a few atomic diameters ? more functionality per mm square More Moore:
  3. 3. Background High Density Integration of semiconductor systems <ul><li>Market issues </li></ul><ul><li>More than Moore </li></ul><ul><ul><li>Europe may take lead in number of market niches - sensing, actuating, optical, display, powering/energy </li></ul></ul><ul><li>Packaging / Back-End is becoming cost driver: </li></ul><ul><ul><ul><li>3D stacking, LED’s, PV, SiP, etc </li></ul></ul></ul><ul><ul><ul><li>Smaller batches, larger flexibility required </li></ul></ul></ul><ul><li>20% energy savings in 2020 </li></ul><ul><li>Market drivers </li></ul><ul><li>Reliability (availability) </li></ul><ul><li>Flexibility (smaller batches) </li></ul><ul><li>Yield (expensive parts) </li></ul><ul><li>Productivity (low CoO) </li></ul>
  4. 4. Background High Density Integration of semiconductor systems Source: University of California
  5. 5. Market drivers for 3D stacking of IC’s. <ul><li>Form Factor Driven </li></ul><ul><li>>2008 </li></ul><ul><li>Achieving the highest </li></ul><ul><li>capacity / volume ratio </li></ul><ul><li>Performance driven </li></ul><ul><li>>2010 </li></ul><ul><li>More than Moore </li></ul><ul><li>Heterogeneous integration </li></ul><ul><li>Interconnect speed and reduced parasitances </li></ul><ul><li>Higher production yield </li></ul><ul><li>Memory </li></ul><ul><li>>2012 </li></ul><ul><li>Flash vs HDD </li></ul><ul><li>HDD roadmap is faster than “Moore’s law”. </li></ul><ul><li>Stacking is extra accelerator for flash </li></ul><ul><li>3D design </li></ul><ul><li>>2016 </li></ul><ul><li>Full 3D design </li></ul><ul><li>Reducing interconnect layers </li></ul><ul><li>Shorter interconnect length </li></ul><ul><li>Limited number of repeaters </li></ul><ul><li>Reduced Si real-estate </li></ul>
  6. 6. Background High Density Integration of semiconductor elements: 3D-TSV TSV creation Carrier bonding Placing Collective bonding Molding Singulation Cleaning Wafer thinning Dicing Picking Inspection TSV filling
  7. 7. General trends related to packaging and assembly <ul><li>Smaller die with low I/O count (  100  m  ) </li></ul><ul><li>Smaller pitch and bumps (  50  m ) </li></ul><ul><li>Thinner dies (  10  m) </li></ul><ul><li>Vertically integrated die </li></ul><ul><ul><li>even smaller pitches and bumps (  1  m ) </li></ul></ul><ul><ul><li>High I/O count (> 10 5 /cm 2 ) </li></ul></ul><ul><ul><ul><li>Homogeneous (memory) </li></ul></ul></ul><ul><ul><ul><li>Heterogeneous (MEMS, Smart Systems) </li></ul></ul></ul>
  8. 8. Cost of ownership 0,00 10,00 20,00 30,00 40,00 50,00 60,00 70,00 80,00 B1 Carrier wafer bonding B2 Thinning B3.1 Application resist B3.2 Patterning B3.3 Development B3.4 DRIE etching B4 TSV filling B5 UBM & bumping B6 Waferprobing B7 Dicing B8 Pick, carrier de-bonding B9 Inspection B10 Place B11 Die bonding B12 Dicing B13 Flip chip or die bonding B14 Encapsulation B15 Singulation B16 End inspection & test B17 Marking B18 Packing Cost of Ownership [$/wafer] Cost of Ownership = 300 $ Cost of Ownership = 150 $
  9. 9. Technologies required (post front-end) <ul><li>New packaging technologies </li></ul><ul><ul><li>Foil (R2R) </li></ul></ul><ul><ul><li>Material deposition (additive interconnect, MID) </li></ul></ul><ul><li>New packaging processes </li></ul><ul><ul><li>Instantaneous on item level </li></ul></ul><ul><ul><li>Batch level </li></ul></ul><ul><li>Material handling </li></ul><ul><ul><li>Fast (price) </li></ul></ul><ul><ul><li>Accurate (sub micron issue) </li></ul></ul><ul><ul><li>New processes (thin die, interconnect) </li></ul></ul><ul><li>New handling technologies </li></ul><ul><ul><li>Silent mechatronics </li></ul></ul><ul><ul><li>In-the-loop optronics </li></ul></ul><ul><ul><li>Smart adhesion </li></ul></ul>Low cost <ul><li>New cost management technologies </li></ul><ul><ul><li>Yield management (in-line probing, cleaning, inspection) </li></ul></ul><ul><ul><li>Small series capability </li></ul></ul>
  10. 10. Pick & Place state-of-the-Art
  11. 11. Typical P&P clycle <ul><li>Move down die: 5 mm </li></ul><ul><li>Place die: 20 ms </li></ul><ul><li>Move op nozzle: 5 mm </li></ul><ul><li>Move nozzle to source wafer: 300 mm </li></ul><ul><li>Move nozzle down to source wafer: 5 mm </li></ul><ul><li>Pick die: 20 ms </li></ul><ul><li>Move up die: 5 mm </li></ul><ul><li>Move die to target wafer: 300 mm </li></ul><ul><li>p 4 = 300 mm, v = 4 m/s, a = 110 m/s 2 , j = 3000 m/s 3 </li></ul>1 2 3 4 5 6 7 8
  12. 12. Accurate and fast Pick & Place Go ==> Look ==> Find ==> Place <ul><li>No or minimal calibration </li></ul><ul><ul><li>Alignment features </li></ul></ul><ul><ul><li>‘ On the fly’ optronics </li></ul></ul><ul><ul><li>Minimal settling times </li></ul></ul><ul><ul><li>Optical resolution at acceptable FOV to match the <1 µm overall placement accuracy </li></ul></ul><ul><ul><li>Adaptive and learning control solutions </li></ul></ul>
  13. 13. Alignment for assembly <ul><li>classical alignment </li></ul><ul><ul><li>Calibrates the ‘complete’ machine </li></ul></ul><ul><li>Main error contributions </li></ul><ul><ul><li>Absolute accuracy of calibration targets (> 1 µ m) </li></ul></ul><ul><ul><li>Rz angle errors caused by pitch, yaw, roll ( ≈ 2 µ m) </li></ul></ul><ul><ul><li>Skew Z axis ( ≈ 2 µ m) </li></ul></ul><ul><ul><li>Tilt during focussing ( ≈ 2.5 µ m) </li></ul></ul><ul><ul><li>Thermal drift </li></ul></ul><ul><li>Conclusion: </li></ul><ul><ul><li>Very difficult to do better than 4 µm </li></ul></ul><ul><ul><li>Concept is complex and not scalable </li></ul></ul>
  14. 14. Alignment concept less is better Simultaneous measurement Of die and substrate <ul><li>Initial placement accuracy < 10 um (3 σ ) </li></ul><ul><li>Placement accuracy in qualification run: </li></ul><ul><ul><li>Standard deviation: < 4.5 um (3 σ ) </li></ul></ul><ul><li>Placement accuracy on calibration unit: </li></ul><ul><ul><li>Standard deviation: < 3.0 um (3 σ ) </li></ul></ul><ul><li>Limitation: mechanical environment </li></ul>
  15. 15. Further developments <ul><li>Roadmap </li></ul><ul><li>Thermal stability </li></ul><ul><ul><li>Better than 10 µm/K/m </li></ul></ul><ul><li>Mechanical stability </li></ul><ul><ul><li>High jerk, a > 100 ms-2, settling time << 20 ms. </li></ul></ul><ul><ul><li>6 DOF </li></ul></ul><ul><ul><li>Balancing and control solutions </li></ul></ul><ul><ul><li>Light and designed stiffness </li></ul></ul><ul><li>Vision controlled motion </li></ul><ul><ul><li>Close loop at >> 5 kHz </li></ul></ul><ul><ul><li>Implementation in P&P machine </li></ul></ul><ul><li>P&P topology for large area placement </li></ul>
  16. 16. P&P topologies
  17. 17. Fluid selfassembly Tolley et al