470 10 Characterization and SpeciﬁcationTable 10.1 Main Speciﬁcation Symbol Unitcharacterization parametersof an analog-to-digital Nominal amplitude resolution N 1converter Sample frequency fs Hz, s−1 Bandwidth BW Hz Integral linearity INL LSB Differential linearity DNL LSB Monotonicity Missing codes Harmonic distortion THD dB Intermodulation distortion IM2,3 dB Spurious-free dynamic range SFDR dB Signal-noise and distortion ratio SINAD dB Signal-noise ratio SNR dB Effective number of bits ENOB 1 Dynamic range DR dB Jitter σt ps Power consumption P W Temperature range T ◦C Power supply VDD V10.1 Test HardwareA correct evaluation of a converter starts at the beginning of the chip design.Interfaces to and from the test equipment must be deﬁned. These analog or digitaldrivers and buffers should not interfere with the test or jeopardize the signal quality.High sampling frequencies require low-jitter buffers and high-frequency analogoutput signals require wide bandwidth buffers. Every experiment starts with a PCBon which the device under test (DUT) is mounted. Some more points must beconsidered when designing a test board:• Analog and digital power supplies and signal sources should be kept separate and only connected together on one single node. Be aware of coupling of earth loops via the mains plug.• Provide sufﬁcient decoupling: microfarad electrolytic capacitors for the low frequencies and metal or ceramic capacitors for the high frequencies. Mount them as close to the package as possible.• In the evaluation phase it may be tempting to use a tool that allows to exchange the samples easily. However, these tools add a lot of distance between the die and the PCB and therefore add many nanohenries of inductance. In Fig. 10.2 a technique is shown where the surface-mounted device is pushed onto the connection electrodes of the printed-circuit card. This setup keeps the distances short.• High-frequency connections must be laid out keeping in mind that every wire is a transmission line. PCB lay-out packages have options to design wires and surrounding grounding in such a way that a deﬁned impedance is achieved.
10.1 Test Hardware 471Fig. 10.1 Test set-up for digital-to-analog conversion• Every signal must be properly terminated close to the test device. This certainly holds for digital signals. Non-terminated digital signals will ring and inject spurious charges into the substrate. A professional measurement setup for characterizing an analog-digital converteruses a computer to control the setup and to analyze the measurement results; seealso the relevant IEEE standardization documents [106–108]. Many professionalevaluation set-ups are constructed with racks of measurement equipment connectedby some interface bus. A computer equipped with test software will control theequipment, setup voltages and currents, step through the signal range, and capturethe data in a data logger of several gigabytes storage. The signal source and thegenerator for the sample rate have to comply to more stringent speciﬁcations thanthe DUT. Modern signal sources are equipped with an extensive user interface,which goes sometimes at the cost of signal distortion and purity. Old “analog”generators are often to be preferred over the modern equipment of the same pricelevel. A well-known method to obtain a high-quality measurement signal usespassive ﬁlters, such as the anti-alias ﬁlter in Fig. 10.1. This setup avoids thatremaining distortion components, noise of various origins as well as cross talk ofthe generators internal processing, disturb the measurement. The analog-to-digitalconverter is normally mounted on a load board: a printed-circuit board adapted forconnection to the main test equipment; see Fig. 10.2. As a direct coupling of theconverter to the test equipment may result in long wires, loading, and ground loops,the (digital) side of the converter is buffered near the device. This buffer will act asa decoupling of signal ringing over the long connection lines. The buffer shieldsthe converter from the high energies that are associated with driving the tester.In extreme cases the connection between the tester and the device is made via anoptical ﬁber, so that a perfect electrical separation between the converter and thetester is achieved. In the tester a data storage device (data logger or data grabber)will store the high-speed data that comes from the converter. The computer can
472 10 Characterization and SpeciﬁcationFig. 10.2 Test board for measuring an analog-to-digital converter (courtesy: R. v. Veldhoven)Fig. 10.3 Measurement setup for a digital-to-analog converterthen in a second phase analyze the data at a convenient speed. The postprocessingresults in an output as shown in Fig. 10.6. An important part of the requirements foranalog-to-digital testing holds similarly for digital-to-analog converters. Figure 10.3shows a potential setup for the test. In accordance with the principle of coherenttesting of the next section, the computer generates and stores a number of datasamples in the storage. A cyclic process reads the data at the desired sample rate andfeeds the digital-to-analog converter. The required measurement equipment mustexceed the speciﬁcations of the to-be-tested device. By applying a passive ﬁlter, themain component of the output signal can be suppressed so that the measurement
10.2 Measurement Methods 473Fig. 10.4 The ﬁrst track-and-hold circuit is tested at high input and high sample rate. The seconddevice runs a sample rate that is an integer factor slower. The resulting output signal containssignals that correspond to the ﬁrst track-and-hold output signal and all harmonicsequipment only needs to have sufﬁcient resolution for the remaining components.The signal analysis will involve a spectrum analyzer or another form of analog-to-digital conversion.Example 10.1. How can a high-speed track-and-hold circuit be tested withouthaving to accurately measure high-frequency output signals?Solution. Subsampling can be used to test a sampling device such as a track-and-hold circuit. Two devices are cascaded as in Fig. 10.4. The ﬁrst device is operatedat a high sample and signal rate. The second track-and-hold circuit samples theoutput of the ﬁrst device at an integer fraction of the sample rate. The original outputsignal of the ﬁrst track-and-hold circuit and its harmonics are subsampled to a lowoutput frequency that can be easily measured. The “subsample” method requiresquite some skills to interpret correctly the resulting frequency components.10.2 Measurement Methods10.2.1 INL and DNLA simple way to evaluate the behavior of a converter is to apply a sawtooth signal tothe input. For converters with speciﬁcations on absolute accuracy a programmablevoltage source is a good choice. Less demanding applications can start with agenerator or a self-built circuit. If the sawtooth is sufﬁciently slow, there willbe enough sample moments to determine the DC parameters as INL, DNL, andmonotonicity. If these parameters need to be established at a 0.1 LSB accuracy level,a data storage of 10 × 2N samples is necessary. A sawtooth signal is not the most critical signal for fast converters and is not easyto generate at high precision. Nyquist analog-to-digital converters with maximuminput frequencies ranging from tens of Megahertz into the Gigahertz range requirethe use of statistical methods. The input signal for measuring dynamic speciﬁcationsis then preferably a sine wave. This test signal can be obtained with a relatively
474 10 Characterization and SpeciﬁcationFig. 10.5 The ideal distribution of hits when a full-scale sine wave is applied to a 5-bit analog-to-digital converterhigh quality through the use of passive ﬁlters. These fast and relatively accuratemethods for determining INL and DNL use the statistical properties of sine waves.When a full-amplitude sine wave with period Tsw is applied to a converter, there isa probability for every code to be hit a number of times. A sine wave will hit morelevels in the upper and lower range than in the middle. If the conversion range isdeﬁned mathematically between 0 and 1, a full-amplitude sine wave takes the form y(t) = 0.5 − 0.5 cos(2π t/Tsw ). (10.1)The signal will go from the lowest level to the highest level in half of a cosineperiod. Δy is a fraction of the range (e.g., 1 LSB) at conversion level y and is calleda “data bin.” Δty is the corresponding fraction of time of the half cosine wave. Δtycorresponds to the hits in bin Δy: while half of the cosine period (Tsw /2) correspondsto the total amount of samples. The ratio Δty /(Tsw /2) is now the fraction of hits thatend up in bin Δy. 1 t= arccos(1 − 2y) ωsw dt 1 = dy ωsw y − y2 Δty 2 dt Δy = Δy = (10.2) Tsw /2 Tsw dy π y − y2Δy is chosen as 1 LSB. Figure 10.5 shows a characteristic distribution of the numberof hits per level or binning of levels. A test run generates the actual measureddistribution of the converted values of a sine wave. This measured distribution iscompared to this theoretical curve, and the deviations (scaled to the same level)result in an INL and DNL plot, as is shown in Fig. 10.6.
10.2 Measurement Methods 475Fig. 10.6 Output of an automated test set-up. Top: histogram output, middle: DNL, bottom: INL This “histogram” method can be used at any frequency. It provides also informa-tion on the linearity problems at higher signal frequencies. The DNL measurementis not optimum as non-monotonicity in this measurement method is not found. Non-monotonicity just changes the DNL value of the corresponding code; the associatedstep back is missed. An additional sawtooth test is required. The calculation abovesuggests that the input amplitude of the sine wave must accurately match the analog-to-digital converter range. In advanced test packages, routines exist that will allowalso amplitudes that extend over the input range. A reconstruction of the input isalso possible; see Fig. 10.7.Example 10.2. How many samples must be acquired to specify the accuracy of theINL with 0.1 LSB?Solution. In the case of an ideal sawtooth the number of samples in a bin with asize of 1 LSB is determined by the slope of the sawtooth. If the sawtooth rises from
476 10 Characterization and SpeciﬁcationFig. 10.7 Reconstructed wave form of a 311 MHz signal sampled at 1.44 Gs/s minimum reference to maximum reference in NST sample periods, then the averagenumber of hits per bin will be NST /2N . In order to obtain an accuracy of 0.1 LSB,NST must exceed 10 × 2N . The above calculation for the histogram method allowsto determine the minimum number of samples that must be generated to get one hitin the middle bin. There the level corresponds to y = 0.5 and hits in bin at y = 0.5 Δty=0.5 Δy Δy 1 = = = = N . (10.3) total samples Tsw /2 π y − y2 π /2 π 2 /2With a sine wave the number of samples is π /2 times larger than when applying asawtooth signal. To obtain an accuracy of 0.1 LSB in INL and DNL a minimum of10 × π 2N /2 samples are required.10.2.2 Harmonic BehaviorThe same sine waves allow to measure harmonic distortion and related qualities(intermodulation, spurious-free dynamic range, etc.) as well as the signal-to-noiseratio. Fourier transformation of the output sample series allows to generate afrequency diagram; Fig. 10.8. Many Fourier algorithms require that the period inwhich the data is measured contains both an integer number of signal periods as wellas an integer number of sample periods; see Fig. 10.9. If this condition is not met,the resulting signal will show side lobes, making the interpretation of the Fourierresult tedious. This phenomenon is called frequency leakage and is illustrated inFig. 10.10. A second pitfall can occur if the sample rate is a simple multiple of the signalfrequency. Under stable signal conditions only a limited number of the levels in theconversion process will be used. The evaluation of the converter is based on therepetition of the same limited sequence of measurements and adds no informationon the levels that are missed; see Fig. 10.11.
10.2 Measurement Methods 477Fig. 10.8 Dynamic measurement of an analog-to-digital converter on intermodulation at f s =100 MHs/sFig. 10.9 The measured period of a signal is expanded on both sides to enable a fouriertransformation. If the signal and the sample frequency do not ﬁt to the window (below) frequencyleakage will occur The basic requirement for a good test that avoids both problems is called the“coherent testing” condition: Ms Msignal Tmeas = = , (10.4) fs fsignal
478 10 Characterization and SpeciﬁcationFig. 10.10 Frequency leakage because of one missing sample: left: 4,000 samples, right plot:3,999 samplesFig. 10.11 If the sample rate is an integer multiple of the sample rate, a part of the measuredsamples are simple duplicates of the earlier sequence. In the frequency domain this may lead to themasking of harmonics behind other harmonics or behind the fundamental frequencywhere Msignal equals the number of input signal periods and Ms the number ofsample periods. If both integers are mutually prime no repetition of test sequenceswill occur. Mutual prime or co-prime means that the largest common divisor ofMsignal and Ms is 1. The total measurement period is given by Tmeas . The measure-ment period is inversely proportional to the frequency resolution or the frequency“binning” of the Fourier transform. It is therefore necessary to choose a sufﬁcientlylarge Msignal , Ms , and Tmeas . The discrete Fourier transform creates Ms /2 + 1 frequency bins of a size1/Tmeas = fs /Ms . Both bins at 0 and at fs /2 are counted. A spectrum analyzeroften provides the option to deﬁne the bin size by means of the “resolutionbandwidth” parameter. If this value is set, automatically the measurement periodwill be adjusted. The energy in the time-discrete signal is distributed over thesefrequency bins. If energies from different phenomena (e.g., a harmonic componentand a folded component) end up in the same bin, the signal strength of thesecomponents will add up or extinguish. A ﬁner frequency grid can be obtained byincreasing the number of samples by increasing the measurement period Tmeas . Figure 10.12 compares spectra taken with 200 and 2,000 samples.Example 10.3. Explain the noise ﬂoor in Fig. 10.12.
10.3 Self Testing 479Fig. 10.12 Increasing the measurement period and the number of samples by a factor of 10,reduces the bin size with that factor and lowers the noise ﬂoor by 10 dBSolution. The 8-bit analog-to-digital converter has a theoretical maximum signal-to-noise ratio of 1.76 + 8×6 dB = 49.8 dB. A measurement and Fourier transformwith 200 samples will result in 101 bins. The quantization energy in Fig. 10.12 isdistributed over these 101 bins, so the “noise ﬂoor” in the spectrum is expected ata 100 × lower energy level: at 49.8 +10 log(100) dB≈ 70 dB below the fundamentalfrequency. A tenfold increase will lead to a 10 times lower amount of energy perbin. In a spectral plot the noise ﬂoor will drop by 10 dB.Example 10.4. An ADC is tested during 1 ms at a sampling speed of 20 Ms/s; theperformance at 3 MHz signal frequency is required. Calculate an appropriate set oftest conditions.Solution. With fs = 20 Ms/s and Tmeas = 1 ms, a total of N = 20, 000 samplesis generated. For a 10-bit ADC this would allow an accuracy of approximately0.1 LSB. A 3 MHz input sine wave would show 3,000 periods, and no coherentconditions can be observed. Changing the input frequency to 2.999 MHz will do. Ata test period of 1 ms, the spectral resolution (frequency bin) is 1/Tmeas = 1 kHz.10.3 Self TestingIn complex systems sometimes forms of self-testing are necessary. Think of sensorsystems that need calibration in places that are difﬁcult to reach. In another examplethere is a liability aspect to the measurement equipment and the usability of theconverter must be established in situ (e.g., in a drilling head at 2 km below the earth’ssurface). Considerations for the implementation of self-test are:• Complexity versus functionality: it may be sufﬁcient to establish correct connec- tivity of the converter. A simple block wave may be sufﬁcient to test.• Independence: no test may lead to a positive result because one error has the same effect on the test circuit as on the converter. Using the same reference for the converter as for the test circuit will disable proper detection of reference deviations.
480 10 Characterization and Speciﬁcation• The cost of error detection are repair facilities present, or can redundancy lead to a solution (e.g., take a two-out-of-three vote).• A parametric test can only be performed if somehow accuracy of the test signal is provided. So self-tests create the need for having somewhere a more accurate reference.Self-testing can be implemented in systems where both a receive and a sendchain are present. In a 2.4 GHz transceiver, such a “loop-back” facility feeds afraction of the transmit power into the receiver. Proper test sequences applied tothe digital-to-analog converter input in the send chain allow a functional self-testand also a few parameters can be evaluated. Another example of self-testing comesfrom systems where it is impossible to approach the converter. For seismic purposesships drag large seismic arrays of cables with sensor interfaces. These arrays spanseveral hundreds of meters. Before a measurement is taken the quality of thetotal interface chain is tested by means of built-in-self-test circuits. It is expectedthat these professional developments of self-testing in some years will result in aconsiderable improvement of the performance of self-test methods.Example 10.5. A 10 bit ADC needs to be tested dynamically at 40 Ms/s in a DSPbased environment. (a) Determine the minimum test time needed to have accessedall codes. (b) Why is it important that all codes have been accessed? There is 1 mstest time available for the FFT. (c) Determine the input frequency at the Nyquistedge for a good test. (d) What is the number of bins in the FFT? (e) Determinethe approximate noise level seen in the FFT plot. (f) What can be the technicaldisadvantage of a long test time?Solution. With 25 ns clock period a ramp signal will take 1024 × 25 ns = 25.6 μs.In case a sinusoidal signal is used 40 μs is needed. Probably the DSP processing willlimit this test. All codes need to be accessed to be sure there are no missing codes.A 1 ms FFT period results in a 1 kHz FFT bin size. For a 40 Ms/s sample rate and a19.999 MHz input signal, N = 40,000 and M = 19.999 which numbers are mutuallyprime. The number of bins in the FFT is 40, 000/2 + 1 = 20,001 bins of 1 kHz. The10-bit converter should have an ideal noise level at 10 × 6 + 1.76 = 62 dB. If thisnoise level is spread over 20,000 bins the level will drop another 1010 log(20, 000) =43 dB. The total quantization noise level can reach −105 dB, so most likely somethermal noise source will dominate. A long test period allows to perform a detailedFFT that may reveal more details of the analog-to-digital converter’s performance.Exercises10.1. Compare the advantages and disadvantages of testing the performance ofan analog-to-digital converter by connecting a high-performance digital-to-analogconverter to the output or by analyzing the digital output in a signal processor.10.2. Propose a sine-based equivalent test method for a digital-to-analog converter.
Exercises 48110.3. The histogram measurement method uses a sine wave. Set up a test schemealong the same lines using a uniform distributed random signal.10.4. Can a sigma–delta modulator be tested with a histogram method?10.5. An 8-bit 20 Ms/s analog-to-digital converter is tested during 0.1 ms with ahalf-scale sine wave. The result is processed via an FFT. Make a drawing of theexpected FFT result.10.6. A 6-bit ADC needs to be tested dynamically at 4 Gs/s in a DSP-basedenvironment. Determine the minimum test time needed to have accessed all codes.There is 40 μs test time available for the FFT. Determine the input frequency at theNyquist edge for a good test. What is the number of bins in the FFT? Determine theapproximate noise level of the FFT.10.7. An 8-bit 600 Ms/s analog-to-digital converter is used in a communicationsystem where a spurious-free dynamic range of 80 dB in 2 MHz bandwidth isrequired. What test is required.10.8. An analog-to-digital converter is part of a system on silicon. The sample clockis generated on chip and cannot be accessed separately. Deﬁne a method to quantifythe jitter of the clock.