A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
• Digital Logic: (1950s-1960s)
A B C Y
0 0 1 1
0 1 0 1
1 1 0 0
0 0 0 1
1 1 1 0
CMOS NAND Gate
Black Box Truth Table Digital Circuit
Sum of Products
Product of Sums
• Regular structures for two-level logic: (1960s-70s)
• Consist of MUXs, De-MUXs, Decoders, FFs.
• Yield spaghetti-like maze!
• Each modification means a new PCB.
• Engineers got fed up!
• Programmable Logic Devices (PLDs): (1970s-80s)
• Chip makers addressed this problem by unconnected arrays of AND-OR
• Fuses used to connect gates.
• Each fuse could be blown open or left close.
• Programming took place at manufacturers plants.
• Simple PLDs (SPLD) could only handle up to 10–20 logic equations.
• You had to break the design apart.
• Wiring was also required and it was a big no-no!
• Again engineers got fed up!
• Complex PLD (CPLD): (1980s)
• Contains a bunch of PLD blocks connected together
by a global interconnect matrix.
• Each component is programmed individually.
• Application Specific Integrated Circuits (ASICs):
• Not available circa 1980s!
• Custom fabricated design from scratch.
• Large complex functions, millions
of gates customised for extreme
speed and low power.
• Very expensive in small
quantities > $1 Million
• Very hard to design.
• NOT reprogrammable which means
• Application Specific Integrated Circuits (ASICs):
• Any mistake means millions of dollars!
• June 1994, a flaw in Intel Pentium chip
causes a division error, discovered by
someone called Dr Nicely.
• December 20th 1994, Intel apologized
and replaced all flawed Pentiums upon request.
• Intel reserved $420 million to cover costs!
• Full story:
•Easy to design
•Millions of gates
•Hard to design
10. FPGA DEFINITIONS
• Field Programmable Gate Arrays (FPGAs) are digital integrated
circuits (ICs) that contain configurable (programmable) blocks
of logic along with configurable interconnects between these
• The “field programmable” portion of the FPGA’s name refers to
the fact that its programming takes place “in the field”.
11. WHY USE FPGA?
• The cost of an FPGA design is much lower than that of an ASIC.
• Implementing design changes is much easier in FPGA.
• Time to market for FPGAs is much faster.
• FPGAs make many small, innovative design companies viable.
• In 2003: 1500 to 4000 ASIC design starts and 5000 ASSP
design starts, while around 450,000 FPGA design starts in the
12. WHY USE FPGA?
• What distinguishes an FPGA from an ASIC is embodied in the
Field P r o g r a m m a b l e Gate Array
13. FPGA ARCHITECTURE
• Programmable logic blocks called
Logic Elements (LEs).
1000+ → 100,000+
• Massive fabric of programmable
• LEs described as islands in a “sea”
• Manufacturers refer to LE in different ways.
Altera refers to it as Adaptive Logic Module (ALM).
Xilinx refers to it as Configurable Logic Block (CLB).
14. ARCHITECTURE: LOGIC ELEMENTS
• 8-input divisible look-up table
• Four dedicated registers to improve
• Full Adders and MUXs.
• 25% of ALMs can be used as
distributed memory using MLABs. ALM for Altera Cyclone V
15. ARCHITECTURE: LUT
• LUT contains memory cells
to implement small
• Each cell holds ‘0’ or ‘1’.
• Programmed with outputs
of truth tables.
• Inputs select content of one
of the cells as output.
16. ARCHITECTURE: LAB AND ALM
• LABs are Logic Array Blocks
• Some FPGAs have two ALMs in each
LAB, while others have four.
• Fast programmable interconnect
within the LAB.
• This is complemented by an
equivalent hierarchy in the
18. ARCHITECTURE: EMBEDDED MULTIPLIERS,
• Some functions may be slow in
• One common operation in DSP
• Some FPGAs provide entire MACs
as embedded functions.
20. DESIGNING WITH FPGA: HDL
• Can’t design FPGA by hand; way too much logic to manage and hard to make changes.
• Hardware Descriptions Languages (HDL) are used to specify functionality of logic at a high
• Most two popular languages are Verilog and VHDL (VHSIC Hardware Description Language).
Verilog VHDL DFF
21. DESIGNING WITH FPGA: FLOW
• High level simulation to catch specification errors.
• Verify pin-outs and connections to other system
• RTL Synthesis:
• Process of compiling HDL code into logic gates
• Technology Mapping:
• Map the logic onto elements available in the implementations
• Placement and Routing:
• Assign logic blocks to functions.
• Make wiring connections.
Place and Rout
22. DESIGNING WITH FPGA: FLOW
• Timing Analysis:
• Verify paths and determine delays.
• Check critical paths and improve their timing.
• Adjust placement of cells to improve timing closure.
• If the design does not fit it can be divided into multiple chips.
• Generate programming files which contain bits to be loaded in
23. DESIGNING WITH FPGA: OPENCL
• What is OpenCL (Open Computing Language)?
• Open standard framework that enables developers to write programs that execute
across heterogeneous systems including CPUs, GPUs, DSPs, and FPGAs.
• Benefits of OpenCL for FPGAs:
• Faster time-to-market: using the OpenCL C-based parallel
programming language as opposed to low-level HDL.
• Quick design exploration: by working at higher
level of abstraction.
• Easy design re-use: by retargeting existing OpenCL
code to current and future FPGAs.
• Faster design completion: by generating an FPGA
implementation in single step.
24. CONFIGURING FPGA
• Millions of SRAM cells hold LUTs and interconnect values.
• Volatile memory, loses configuration when power is turned off.
• Non-volatile memories are used to power up FPGAs with
specific bit file.
25. SoC FPGA
• Formerly, designers used to implement what so called soft
processors, which are microprocessors implemented in HDL.
• Popular IPs: NIOS II from Altera and MicroBlaze from Xilinx.
• Such architectures did not realize high performances, in
addition to resources consumption and power consumption.
• They were also vendor-specific.
26. SoC FPGA
• Chip makers again for the rescue!
• SoC FPGAs integrate an ARM-based hard
processor system (HPS) consisting of
processor, peripherals, and memory
interfaces with the FPGA fabric using
a high bandwidth interconnect backbone.
• It combines the performance and power
savings of hard intellectual property (IP)
with the flexibility of programmable logic.
27. SoC FPGA: ADVANTAGES
• Improved system performance: through a higher HPS to FPGA bandwidth
interconnect, hardware acceleration, and increased memory performance.
• Increased reliability: through error correction code (ECC) and memory
protection. Warm/Cold CPU reset that initiates without affecting or
• More flexibility: through hardware differentiation, system boot and
configurations options, and multiple hardened memory controllers.
• Lower system cost: through single-chip integration, integrated PCIe
controller and no power off sequencing.
28. SoC FPGA
• FPGA Vendors and Processors:
FPGA Vendor Hard Processor Soft Processor
Actel None Third-Party only
Altera ARM NIOS, NIOS II
Lattice None Third-Party only
Xilinx IBM PowerPC MicroBlaze, PicoBlaze
QuickLogic MIPS Third-Party only
30. SoC FPGA: HPS FEATURES
• 925 MHz, dual-core ARM® Cortex™-A9 MPCore™ processor.
• Each processor core includes:
• 32 KB of L1 instruction cache, 32 KB of L1 data cache.
• Single- and double-precision floating-point unit and NEONTM media
• CoreSightTM debug and trace technology.
• 512 KB of shared L2 cache.
• 64 KB of scratch RAM.
• Multiport SDRAM controller with support for DDR2, DDR3, and
LPDDR2 and optional error correction code (ECC) support.
31. SoC FPGA: APPLICATIONS
• Just to name a few:
• Automotive Advanced Driver Assistance Systems (ADAS)
• Wireless Communications
• Military Radar
• Military Secure Communications
• The top four manufacturers of electronic imaging systems all use FPGAs
• This include CT, MRI, and Ultrasonic equipment