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Dos final ppt


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Dos final ppt

  2. 2. TOPICS TO BE COVERED: <ul><li>DSM system </li></ul><ul><li>Shared memory </li></ul><ul><li>On chip memory </li></ul><ul><li>Bus based multiprocessor </li></ul><ul><li>Working through cache </li></ul><ul><li>Write through cache </li></ul><ul><li>Write once protocol </li></ul><ul><li>Ring based multiprocessor </li></ul><ul><li>Protocol used </li></ul><ul><li>Similarities and differences bw ring based and bus based </li></ul>
  3. 3. What is a DSM system? <ul><li>A distributed-memory system (often called a multicomputer) consist of collection of workstations connected by a LAN share a single paged,virtual address space </li></ul><ul><li>Each page is present on exactly one maachine </li></ul><ul><li>An attempt to reference a page on different machine causes a hardware page fault which traps to operating system </li></ul><ul><li>The OS den sends a message to the remote machinewhich finds the needed page and sends it back to the req. processor </li></ul>
  4. 4. What is shared memory? <ul><li>Shared memory is the memory that is simultaneously accessed by more than one CPU OR PROCCESSOR </li></ul><ul><li>There are local caches for each processor </li></ul><ul><li>It is cheaper to cache than main memory </li></ul><ul><li>It is simple to program and hard to scale </li></ul>
  5. 5. Various architectures to be discussed: <ul><li>On chip memory </li></ul><ul><li>Bus based multiprocessors </li></ul><ul><li>Ring based multiprocessors </li></ul>
  6. 6. On Chip Memory <ul><li>In this CPU portion of the chip has a address and data lines that directly connect to the memory portion </li></ul><ul><li>Such chips are used in cars,appliances and even toys </li></ul><ul><li>In hypothetical shared memory multiprocessor we have multiple CPU’S directly sharing the same memory but it would be complicated n expensive </li></ul>
  7. 7. <ul><li>On-Chip Memory </li></ul>CPU Memory CPU1 Memory CPU4 CPU2 CPU3 Chip package Address and data lines Connecting the CPU to the memory extension A single-chip computer A hypothetical shared-memory Multiprocessor.
  8. 8. What is a bus??? <ul><li>BUS is a collection of parallel wires,some holding the address the CPU wants to read or write,some for sending or receiving data and the rest for controlling the transfers. </li></ul><ul><li>In most systems buses are external and are used to connect CPU’S,MEMORIES AND I/O CONTROLLERS </li></ul>
  9. 9. Bus-based multiprocessors Bus-based multiprocessors BUS BASED MULTIPROCESSORS SMP : Symmetric Multi-Processing All CPUs connected to one bus (backplane) Memory and peripherals are accessed via shared bus. System looks the same from any processor. Bus CPU A CPU B memory Device I/O
  10. 10. Bus-based multiprocessors Dealing with bus overload - add local memory CPU does I/O to cache memory - access main memory on cache miss Bus memory Device I/O CPU A cache CPU B cache
  11. 11. Working with a cache CPU A reads location 12345 from memory Bus 12345:7 Device I/O CPU A 12345: 7 CPU B
  12. 12. Working with a cache CPU B reads location 12345 from memory Gets old value Memory not coherent! Bus 12345:7 Device I/O CPU A 12345: 3 CPU B 12345: 7
  13. 13. Write-through cache … continued CPU B reads location 12345 from memory - loads into cache Bus 12345:3 Device I/O CPU A 12345: 3 CPU B 12345: 3
  14. 14. Write-through cache CPU A modifies location 12345 - write-through 12345:3 12345: 3 Cache on CPU B not updated Memory not coherent! Bus Device I/O CPU A CPU B 12345: 3 12345:0 12345: 0
  15. 15. Write once protocol <ul><li>This protocol manages cache blocks, each of which can be in one of the following three states: </li></ul><ul><li>INVALID: This cache block does not contain valid data. </li></ul><ul><li>CLEAN: Memory is up-to-date; the block may be in other caches. </li></ul><ul><li>DIRTY: Memory is incorrect; no other cache holds the block. </li></ul><ul><li>The basic idea of the protocol is that a word that is being read by multiple CPUs is allowed to be present in all their caches. A word that is being heavily written by only one machine is kept in its cache and not written back to memory on every write to reduce bus traffic. </li></ul>
  16. 16. Write through protocol Event Action taken by a cache in response to its own CPU’s operation Action taken by a cache in response to a remote CPU’s operation Read mis s Fetch data from memory and store in cache no action Read hit Fetch data from local cache no action Write miss Update data in memory and store in cache no action Write hit Update memory and cache invalidate cache entry
  17. 17. For example A B W 1 C W 1 CLEAN Memory is correct <ul><li>Initial state – word W 1 containing </li></ul><ul><li>value W1 is in memory and is also </li></ul><ul><li>cached by B. </li></ul>CPU A B W 1 C W 1 W 1 CLEAN CLEAN Memory is correct (b) A reades word W and gets W 1 . B does not respond to the read, but the memory does.
  18. 18. A B W 1 C W 2 W 1 A B W 1 C W 3 W 1 DIRTY INVALID DIRTY INVALID Memory is correct (c)A write a value W2, B snoops on the bus, sees the write, and invalidates its entry. A’s copy is marked DIRTY. Not update memory Memory is correct (d) A write W again. This and subsequent writes by A are done locally, without any bus traffic.
  19. 19. A B W 1 C W 3 W 1 INVALID INVALID DIRTY W 3 (e) C reads or writes W. A sees the request by snooping on the bus, provides the value, and invalidates its own entry. C now has the only valid copy. Not update memory
  20. 20. Ring-Based Multiprocessors : Memnet CPU CPU CPU CPU CPU CPU CPU Private memory MMU Cache Home memory Memory management unit Location Interrupt Home Exclusive Valid 0 1 2 3 The block table
  21. 21. Protocol <ul><li>Read </li></ul><ul><li>When the CPU wants to read a word from shared memory, the memory address to be read is passed to the Memnet device, which checks the block table to see if the block is present. If so, the request is satisfied. If not, the Memnet device waits until it captures the circulating token, puts a request onto the ring. As the packet passes around the ring, each Memnet device along the way checks to see if it has the block needed. If so, it puts the block in the dummy field and modifies the packet header to inhibit subsequent machines from doing so. </li></ul><ul><li>If the requesting machine has no free space in its cache to hold the incoming block, to make space, it picks a cached block at random and sends it home. Blocks whose Home bit are set are never chosen because they are already home. </li></ul>
  22. 22. <ul><li>Write </li></ul><ul><li>If the block containing the word to be written is present and is the only copy in the system (i.e., the Exclusive bit is set), the word is just written locally . </li></ul><ul><li>If the needed block is present but it is not the only copy, an invalidation packet is first sent around the ring to force all other machines to discard their copies of the block about to be written. When the invalidation packet arrives back at the sender, the Exclusive bit is set for that block and the write proceeds locally . </li></ul><ul><li>If the block is not present, a packet is sent out that combines a read request and an invalidation request. The first machine that has the block copies it into the packet and discards its own copy. All subsequent machines just discard the block from their caches. When the packet comes back to the sender, it is stored there and written . </li></ul>
  23. 23. Similarities bw bus based and ring based multiprocessors <ul><li>In both cases read operations always return the values most recently written </li></ul><ul><li>In both designs a block may be absent from a cache,present in multiple caches for reading,or present in a single cache for writing </li></ul>
  24. 24. DIFFERENCES BW TWO MULTIPROCESSORS <ul><li>BUS BASED MULTIPROCCESORS </li></ul><ul><li>They are tightly coupled with the CPU’S normally in a single rack </li></ul><ul><li>It has seprate global memory </li></ul><ul><li>RING BASED MULTIPROCCESORS </li></ul><ul><li>Machines here can be much more loosely coupled n this loose coupling can affect their performance </li></ul><ul><li>It has no seprate global memory </li></ul>
  25. 25. The end.