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cs8421_lect_02_fall0..

  1. 1. 8-11-2007 <ul><li>Class </li></ul><ul><ul><ul><li>Will </li></ul></ul></ul><ul><ul><ul><ul><ul><li>Start </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Momentarily… </li></ul></ul></ul></ul></ul>(Lecture 2) CS8421 Computing Systems Dr. Jose M. Garrido
  2. 2. Real-Time Applications and Examples <ul><li>Vehicle systems </li></ul><ul><li>Traffic control </li></ul><ul><li>Process control </li></ul><ul><li>Medical systems </li></ul><ul><li>Military RT systems </li></ul><ul><li>Manufacturing Robots systems </li></ul><ul><li>Security control </li></ul><ul><li>Telecommunication systems </li></ul><ul><li>Computer games </li></ul><ul><li>Multimedia systems </li></ul><ul><li>Household appliance monitoring & control </li></ul><ul><li>Building energy control </li></ul>
  3. 3. Properties of Real-Time Systems <ul><li>Timeliness - the system must perform operations in timely manner </li></ul><ul><li>Reactiveness - the system continuously responds to (random) events </li></ul><ul><li>Concurrency - multiple simultaneous activities are carried out </li></ul><ul><li>Distribution - tasks cooperate in multiple computing sites </li></ul>
  4. 4. RTS Time Issues <ul><li>The goal is to reduce two specific intervals: </li></ul><ul><ul><li>service time - the interval taken to compute a response to a given input </li></ul></ul><ul><ul><li>latency - the interval between the time of occurrence of an input and the time at which it starts being serviced </li></ul></ul><ul><li>The sum of these two intervals represents the response time . This must be shorter than the deadline for this type of input. </li></ul>
  5. 5. Architecture <ul><li>Architecture refers to the attributes visible to the programmer </li></ul><ul><ul><li>Instruction set </li></ul></ul><ul><ul><li>Number of bits used for data representation </li></ul></ul><ul><ul><li>I/O mechanisms </li></ul></ul><ul><ul><li>Addressing techniques. </li></ul></ul><ul><li>Is there a multiply instruction? </li></ul>
  6. 6. Organization <ul><li>Organization refers to how features are implemented </li></ul><ul><ul><li>Control signals </li></ul></ul><ul><ul><li>Interfaces </li></ul></ul><ul><ul><li>Memory technology. </li></ul></ul><ul><li>Is there a hardware multiply unit or is it done by repeated addition? </li></ul>
  7. 7. Architecture & Organization <ul><li>All Intel x86 family share the same basic architecture </li></ul><ul><li>The IBM System/370 family share the same basic architecture </li></ul><ul><li>This gives code compatibility </li></ul><ul><ul><li>At least backwards </li></ul></ul><ul><li>Organization differs between different versions </li></ul>
  8. 8. Structure & Function <ul><li>Structure is the way in which components relate to each other </li></ul><ul><li>Function is the operation of individual components as part of the structure </li></ul>
  9. 9. Computer Architecture Overview <ul><li>Components of a computer system: </li></ul><ul><li>CPU </li></ul><ul><li>Main Memory </li></ul><ul><li>Secondary Storage </li></ul><ul><li>I/O Devices </li></ul><ul><li>Bus </li></ul><ul><li>Operating System </li></ul>
  10. 10. General System Structure
  11. 11. Computer Functions <ul><li>The computer functions are: </li></ul><ul><li>Data processing </li></ul><ul><li>Data storage (memory) </li></ul><ul><li>Data movement (I/O) </li></ul><ul><li>Control </li></ul>
  12. 12. Computer Functional View
  13. 13. Data Movement
  14. 14. Data Storage
  15. 15. Processing from/to Storage
  16. 16. Processing from Storage to I/O
  17. 17. Structure - Top Level Computer Main Memory Input Output Systems Interconnection Peripherals Communication lines Central Processing Unit Computer
  18. 18. Structure - The CPU Computer Arithmetic and Logic Unit Control Unit Internal CPU Interconnection Registers CPU I/O Memory System Bus CPU
  19. 19. Structure - The Control Unit CPU Control Memory Control Unit Registers and Decoders Sequencing Logic Control Unit ALU Registers Internal Bus Control Unit
  20. 20. ENIAC - background <ul><li>Electronic Numerical Integrator And Computer </li></ul><ul><li>Eckert and Mauchly </li></ul><ul><li>University of Pennsylvania </li></ul><ul><li>Trajectory tables for weapons </li></ul><ul><li>Started 1943 </li></ul><ul><li>Finished 1946 </li></ul><ul><ul><li>Too late for war effort </li></ul></ul><ul><li>Used until 1955 </li></ul>
  21. 21. ENIAC - Details <ul><li>Decimal (not binary) </li></ul><ul><li>20 accumulators of 10 digits </li></ul><ul><li>Programmed manually by switches </li></ul><ul><li>18,000 vacuum tubes </li></ul><ul><li>30 tons </li></ul><ul><li>15,000 square feet </li></ul><ul><li>140 kW power consumption </li></ul><ul><li>5,000 additions per second </li></ul>
  22. 22. von Neumann/Turing <ul><li>Stored Program concept </li></ul><ul><li>Main memory store programs and data </li></ul><ul><li>ALU operating on binary data and binary code </li></ul><ul><li>Control unit interpreting instructions from memory and executing </li></ul><ul><li>Input and output equipment operated by control unit </li></ul><ul><li>Princeton Institute for Advanced Studies </li></ul><ul><ul><li>IAS </li></ul></ul><ul><li>Completed 1952 </li></ul>
  23. 23. Structure of von Neumann Machine
  24. 24. IAS - details <ul><li>1000 x 40 bit words </li></ul><ul><ul><li>Binary number </li></ul></ul><ul><ul><li>2 x 20 bit instructions </li></ul></ul><ul><li>Set of registers (storage in CPU) </li></ul><ul><ul><li>Memory Buffer Register </li></ul></ul><ul><ul><li>Memory Address Register </li></ul></ul><ul><ul><li>Instruction Register </li></ul></ul><ul><ul><li>Instruction Buffer Register </li></ul></ul><ul><ul><li>Program Counter </li></ul></ul><ul><ul><li>Accumulator </li></ul></ul><ul><ul><li>Multiplier Quotient </li></ul></ul>
  25. 25. Structure of IAS – detail
  26. 26. Functioning of the IAS Computer <ul><li>Repetitively performing an instruction cycle </li></ul><ul><li>An instruction cycle has two subcycles </li></ul><ul><ul><li>Fetch cycle – the “opcode” of instruction and its address are loaded into registers IR and MAR </li></ul></ul><ul><ul><li>Execute cycle -- interpretation of the “opcode” and execution of the instruction </li></ul></ul>
  27. 27. Instructions of the IAS Computer <ul><li>The IAS computer had 21 instructions </li></ul><ul><li>These instructions are grouped as: </li></ul><ul><ul><li>Data transfer </li></ul></ul><ul><ul><li>Unconditional branch </li></ul></ul><ul><ul><li>Conditional branch </li></ul></ul><ul><ul><li>Arithmetic </li></ul></ul><ul><ul><li>Address modify </li></ul></ul>
  28. 28. Commercial Computers <ul><li>1947 - Eckert-Mauchly Computer Corporation </li></ul><ul><li>UNIVAC I (Universal Automatic Computer) </li></ul><ul><li>US Bureau of Census 1950 calculations </li></ul><ul><li>Became part of Sperry-Rand Corporation </li></ul><ul><li>Late 1950s - UNIVAC II </li></ul><ul><ul><li>Faster </li></ul></ul><ul><ul><li>More memory </li></ul></ul>
  29. 29. IBM <ul><li>Punched-card processing equipment </li></ul><ul><li>1953 - the 701 </li></ul><ul><ul><li>IBM’s first stored program computer </li></ul></ul><ul><ul><li>Scientific calculations </li></ul></ul><ul><li>1955 - the 702 </li></ul><ul><ul><li>Business applications </li></ul></ul><ul><li>Lead to 700/7000 series </li></ul><ul><li>The IBM 7094 introduced the data channel, a smaller specialized I/O processor </li></ul>
  30. 30. Transistors <ul><li>Replaced vacuum tubes </li></ul><ul><li>Smaller </li></ul><ul><li>Cheaper </li></ul><ul><li>Less heat dissipation </li></ul><ul><li>Solid State device </li></ul><ul><li>Made from Silicon (Sand) </li></ul><ul><li>Invented 1947 at Bell Labs </li></ul><ul><li>William Shockley et al. </li></ul>
  31. 31. Transistor Based Computers <ul><li>Second generation machines </li></ul><ul><li>NCR & RCA produced small transistor machines </li></ul><ul><li>IBM 7000 </li></ul><ul><li>DEC - 1957 </li></ul><ul><ul><li>Produced PDP-1 </li></ul></ul>
  32. 32. Microelectronics <ul><li>Literally - “small electronics” </li></ul><ul><li>A computer is made up of gates, memory cells and interconnections </li></ul><ul><li>These can be manufactured on a semiconductor </li></ul><ul><li>e.g. silicon wafer </li></ul><ul><li>Used in the third generation of computers </li></ul>
  33. 33. Generations of Electronics <ul><li>Vacuum tube - 1946-1957 </li></ul><ul><li>Transistor - 1958-1964 </li></ul><ul><li>Small scale integration - 1965 on </li></ul><ul><ul><li>Up to 100 devices on a chip </li></ul></ul><ul><li>Medium scale integration - to 1971 </li></ul><ul><ul><li>100-3,000 devices on a chip </li></ul></ul><ul><li>Large scale integration - 1971-1977 </li></ul><ul><ul><li>3,000 - 100,000 devices on a chip </li></ul></ul><ul><li>Very large scale integration - 1978 to date </li></ul><ul><ul><li>100,000 - 100,000,000 devices on a chip </li></ul></ul><ul><li>Ultra large scale integration </li></ul><ul><ul><li>Over 100,000,000 devices on a chip </li></ul></ul>
  34. 34. Moore’s Law <ul><li>Increased density of components on chip </li></ul><ul><li>Gordon Moore - cofounder of Intel </li></ul><ul><li>Number of transistors on a chip will double every year </li></ul><ul><li>Since 1970’s development has slowed a little </li></ul><ul><ul><li>Number of transistors doubles every 18 months </li></ul></ul><ul><li>Cost of a chip has remained almost unchanged </li></ul><ul><li>Higher packing density means shorter electrical paths, giving higher performance </li></ul><ul><li>Smaller size gives increased flexibility </li></ul><ul><li>Reduced power and cooling requirements </li></ul><ul><li>Fewer interconnections increases reliability </li></ul>
  35. 35. Growth in CPU Transistor Count
  36. 36. IBM 360 series <ul><li>1964 </li></ul><ul><li>Replaced (& not compatible with) 7000 series </li></ul><ul><li>First planned “family” of computers </li></ul><ul><ul><li>Similar or identical instruction sets </li></ul></ul><ul><ul><li>Similar or identical O/S </li></ul></ul><ul><ul><li>Increasing speed </li></ul></ul><ul><ul><li>Increasing number of I/O ports (i.e. more terminals) </li></ul></ul><ul><ul><li>Increased memory size </li></ul></ul><ul><ul><li>Increased cost </li></ul></ul><ul><li>Multiplexed switch structure </li></ul>
  37. 37. DEC PDP-8 <ul><li>1964 </li></ul><ul><li>First minicomputer </li></ul><ul><li>Did not need air conditioned room </li></ul><ul><li>Small enough to sit on a lab bench </li></ul><ul><li>$16,000 </li></ul><ul><ul><li>$100k+ for IBM 360 </li></ul></ul><ul><li>Embedded applications & OEM </li></ul><ul><li>BUS STRUCTURE </li></ul>
  38. 38. DEC - PDP-8 Bus Structure OMNIBUS Console Controller CPU Main Memory I/O Module I/O Module
  39. 39. Semiconductor Memory <ul><li>1970 </li></ul><ul><li>Fairchild </li></ul><ul><li>Size of a single core </li></ul><ul><ul><li>i.e. 1 bit of magnetic core storage </li></ul></ul><ul><li>Holds 256 bits </li></ul><ul><li>Non-destructive read </li></ul><ul><li>Much faster than core </li></ul><ul><li>Capacity approximately doubles each year </li></ul>
  40. 40. Intel <ul><li>1971 - 4004 </li></ul><ul><ul><li>First microprocessor </li></ul></ul><ul><ul><li>All CPU components on a single chip </li></ul></ul><ul><ul><li>4 bit </li></ul></ul><ul><li>Followed in 1972 by 8008 </li></ul><ul><ul><li>8 bit </li></ul></ul><ul><ul><li>Both designed for specific applications </li></ul></ul><ul><li>1974 - 8080 </li></ul><ul><ul><li>Intel’s first general purpose microprocessor </li></ul></ul>
  41. 41. Improving Speed <ul><li>Pipelining </li></ul><ul><li>On board cache </li></ul><ul><li>On board L1 & L2 cache </li></ul><ul><li>Branch prediction </li></ul><ul><li>Data flow analysis </li></ul><ul><li>Speculative execution </li></ul>
  42. 42. Performance Mismatch <ul><li>Processor speed increased </li></ul><ul><li>Memory capacity increased </li></ul><ul><li>Memory speed lags behind processor speed </li></ul>
  43. 43. DRAM and Processor Characteristics
  44. 44. Trends in DRAM use
  45. 45. Pentium Evolution (1) <ul><li>8080 </li></ul><ul><ul><li>first general purpose microprocessor </li></ul></ul><ul><ul><li>8 bit data path </li></ul></ul><ul><ul><li>Used in first personal computer – Altair </li></ul></ul><ul><li>8086 </li></ul><ul><ul><li>much more powerful </li></ul></ul><ul><ul><li>16 bit </li></ul></ul><ul><ul><li>instruction cache, prefetch few instructions </li></ul></ul><ul><ul><li>8088 (8 bit external bus) used in first IBM PC </li></ul></ul><ul><li>80286 </li></ul><ul><ul><li>16 Mbyte memory addressable </li></ul></ul><ul><ul><li>up from 1Mb </li></ul></ul><ul><li>80386 </li></ul><ul><ul><li>32 bit </li></ul></ul><ul><ul><li>Support for multitasking </li></ul></ul>
  46. 46. Pentium Evolution (2) <ul><li>80486 </li></ul><ul><ul><li>sophisticated powerful cache and instruction pipelining </li></ul></ul><ul><ul><li>built in maths co-processor </li></ul></ul><ul><li>Pentium </li></ul><ul><ul><li>Superscalar </li></ul></ul><ul><ul><li>Multiple instructions executed in parallel </li></ul></ul><ul><li>Pentium Pro </li></ul><ul><ul><li>Increased superscalar organization </li></ul></ul><ul><ul><li>Aggressive register renaming </li></ul></ul><ul><ul><li>branch prediction </li></ul></ul><ul><ul><li>data flow analysis </li></ul></ul><ul><ul><li>speculative execution </li></ul></ul>
  47. 47. Pentium Evolution (3) <ul><li>Pentium II </li></ul><ul><ul><li>MMX technology </li></ul></ul><ul><ul><li>graphics, video & audio processing </li></ul></ul><ul><li>Pentium III </li></ul><ul><ul><li>Additional floating point instructions for 3D graphics </li></ul></ul><ul><li>Pentium 4 </li></ul><ul><ul><li>Note Arabic rather than Roman numerals </li></ul></ul><ul><ul><li>Further floating point and multimedia enhancements </li></ul></ul><ul><li>Itanium </li></ul><ul><ul><li>64 bits </li></ul></ul>
  48. 48. PowerPC <ul><li>IBM, Motorola, Apple </li></ul><ul><li>Used in Apple Macintosh </li></ul><ul><li>RISC architecture </li></ul><ul><ul><li>601 </li></ul></ul><ul><ul><li>603 </li></ul></ul><ul><ul><li>604 </li></ul></ul><ul><ul><li>620 </li></ul></ul><ul><ul><li>740/750 (G3) </li></ul></ul><ul><ul><li>G4 </li></ul></ul><ul><ul><li>G5 </li></ul></ul>
  49. 49. What is a Program? <ul><li>A sequence of steps (instructions?) </li></ul><ul><li>For each step, an arithmetic or logical operation is carried out </li></ul><ul><li>For each operation, a different set of control signals is needed </li></ul>
  50. 50. Function of Control Unit <ul><li>For each operation a unique operation code is provided </li></ul><ul><ul><li>e.g. ADD, MOVE </li></ul></ul><ul><li>A hardware segment accepts the code and issues the control signals </li></ul><ul><li>This is the foundation for a computer! </li></ul>
  51. 51. Components <ul><li>The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit </li></ul><ul><li>Data and instructions need to get into the system and results out </li></ul><ul><ul><li>Input/output </li></ul></ul><ul><li>Temporary storage of code and results is needed </li></ul><ul><ul><li>Main memory </li></ul></ul>
  52. 52. Components: Top Level View
  53. 53. Instruction Cycle <ul><li>Two steps: </li></ul><ul><ul><li>Fetch </li></ul></ul><ul><ul><li>Execute </li></ul></ul>
  54. 54. Fetch Cycle <ul><li>Program Counter (PC) holds address of next instruction to fetch </li></ul><ul><li>Processor fetches instruction from memory location pointed to by PC </li></ul><ul><li>Increment PC </li></ul><ul><ul><li>Unless told otherwise </li></ul></ul>
  55. 55. Execute Cycle <ul><li>Instruction loaded into Instruction Register (IR) </li></ul><ul><li>Processor interprets instruction and performs required actions </li></ul>
  56. 56. Categories of Actions <ul><li>Processor-memory </li></ul><ul><ul><li>data transfer between CPU and main memory </li></ul></ul><ul><li>Processor I/O </li></ul><ul><ul><li>Data transfer between CPU and I/O module </li></ul></ul><ul><li>Processing </li></ul><ul><ul><li>Some arithmetic or logical operation on data </li></ul></ul><ul><li>Control </li></ul><ul><ul><li>Alteration of sequence of operations </li></ul></ul><ul><ul><li>e.g. jump </li></ul></ul><ul><li>Combination of above </li></ul>
  57. 57. Fetch/Decode/Execute/Interrupt Cycle <ul><li>Instruction Fetch . The number of processor/bus cycles required depends on the width of the instruction and the width of the bus </li></ul><ul><li>Decode . Determine what the instruction will actually do, in particular, what operands are required before the instruction can execute </li></ul><ul><li>Operand Fetch - multiple operands may require multiple fetches </li></ul><ul><li>Execute Instruction </li></ul><ul><li>Check for Interrupts. </li></ul>
  58. 58. Example of Execution <ul><li>The processor has a single data register, the accumulator, AC </li></ul><ul><li>Both instructions and data are 16 bits long </li></ul><ul><li>Instruction format: </li></ul><ul><ul><li>4 bits for the opcode, for 16 different opcodes </li></ul></ul><ul><ul><li>12 bits for the address (4K) </li></ul></ul><ul><li>Opcodes: 1=load AC, 2=store AC, 5= add to AC </li></ul><ul><li>Instruction format using Hex notation </li></ul>
  59. 59. Example of Program Execution
  60. 60. End of Lecture <ul><li>End </li></ul><ul><li>Of </li></ul><ul><li>Today’s </li></ul><ul><li>Lecture. </li></ul><ul><li>8-21-07 </li></ul>

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