Making of an Application Specific Integrated Circuit
THE MAKING OF AN ASICThe process of designing and productionising a mixed signalapplication specific integrated circuit with SWINDON Silicon Systemswww.swindonsilicon.co.uk
ContentsAn informative guide tothe process of designingand productionising amixed signalapplication specificintegrated circuitwithSWINDON Silicon SystemsProductionQualificationTest DevelopmentEvaluationProcessingDesign and LayoutSpecificationThe Design Process
The Design Process - Part 1The ASIC Development Process provides a provenroadmap for complete Product Development1. Application Review Review of your system requirements Establish ASIC requirements2. ASIC Quotation Non-Recurring Engineering (NRE) Estimated Unit Price (in Production) Development Schedule3. Preliminary Design Review Review Block Diagram Establish Specification Establish Packaging Requirements Establish Test Requirements Review Schedule Establish Target Die Size Establish Fabrication Process4. Initial Design & Layout Complete Critical Circuits design Complete preliminary ASIC Floor Plan Complete Built-In Test features5. Critical Design Review Review Critical Circuit performance Report physical layout status6. Final Design & Layout Complete Cell Level designs Complete Top Level design Simulate over temperature | voltage Complete Design Rule Checks (DRCs) Complete Layout vs. Schematic (LVS) Prepare Test Plans
The Design Process – Part 2The ASIC Development Process provides a provenroadmap for complete Product Development7. Final Design Review Review Simulations Review Test Plans Review Physical Layout Proceed to Fabrication8. Prototype Fabrication Mask Fabrication Silicon Fabrication9. Test Program Development Prototype Test Program Preliminary Production Test Program10. Prototype Evaluation SWINDON tests Prototype at waferprobe SWINDON tests Prototype inpackage Customer evaluates Prototype11. Prototype Acceptance Review ASIC performance versusSpecification Reliability Testing Review Yield Analysis Review Proceed to Production
The Importance of SpecificationThe specification phase is an extremelyimportant part of the design process as anyerrors that occur here will be magnifiedfurther down the process.That is why SWINDON assists its customers indeveloping the systems specification andadvises as to what can be achieved on chip.The full ASIC specification is then producedby the relevant SWINDON technical leadengineer and this will be signed off by allparties concerned.This extensive process usually takesbetween 4 and 12 weeks depending uponthe complexity of the device that is beingdesigned.
The Specification Process1. Review of the system schematics, blockdiagrams and specifications.2. Develop an understanding of the designchallenges, operating environment andregulatory requirements3. Understand the final product (not just theASIC) including any certificationrequirements such as IEC, TS compliance.4. Produce an ASIC block diagram and fullspecification that states full operationalparameters and pin out and any requiredexternal components.5. Identify board level architectural trade-offs that lead to most cost effective siliconintegration.
DesignA simplistic example1 • Assign Technical Lead, Project Manager and Design Team2 • Determine process3 • System level design, block specification and Floor plan4 • Block level design/simulation and IP block insertion5 • Design for Test (DFT)6 • Synthesis and verification7 • Layout8 • DRC and LVS9 • Tapeout
1. Design and LayoutSystem leveldesign blockspecification• A top down design approach is adopted for the Project• Partitioning the chip into functional blocks• Defining their functionality and writing a specification foreach block• Writing a behavioural model (analogue or digital), which isused to verify that the design meets its requirements.• Writing a simulation plan which describes the method ofproving the design correctnessFloor plan• A top level chip floor plan is produced that defines the areaand shape of each functional block. Along with itsinterconnection to other blocks. The block areas are designgoals for each block. These terms will be assessed and thefloor plan updated as the project progresses.
2. Design and LayoutFor mixed signal designs there are2 procedures run in parallel: Analogue | DigitalBlock level design /simulation• Analogue Design• Circuit blocks are designed at the transistorlevel and simulated using a HSPICEcompatible simulator.• Simulation results are verified against theblock specification and the VerilogAbehavioural model.• Digital Design• Writing a synthesizable RTL (registertransfer level) description (either onVerilog or VHDL) of the device.• Writing a behavioural model, which is usedto verify that the design meets itsrequirements.• Writing a verification plan and acorresponding verification environmentwhich describes and implements themethod of proving the design correctness
3. Design and LayoutVerification• The RTL description is verifiedagainst the behavioural model.• This approach reduces theprobability of the design errorsince no RTL designer tests hisown code.
4. Design and LayoutDesign for Test(DFT)•Most mixed signal ASIC designs are complex require builtin assistance in order to be able to production testeffectively. These preparations are called DFT (design fortest).•For the analogue sections it is important that key signalscan be observed in the analogue blocks. This may requirethe routing of internal test points to device pads.•For the Digital section of the design DFT techniquesinclude:•Scan path insertion - a methodology of linking allregisters into one long shift register (scan path). This canbe used to check small parts of design instead of thewhole design (the latter being almost alwaysimpossible).•BIST (built-in self test) - a device used to check RAMs.After being triggered it feeds specific test patterns to theRAM module, reads back and compares results.•ATPG (automatic test pattern generation) - a method ofcreating test vectors for scan paths and BISTautomatically. Most modern EDA tool chainsincorporate such a feature.
5. Design and LayoutSynthesis• The synthesizable and verified RTL undergo logic synthesis. Thesynthesized reads RTL input, user-specified constraints and acell library from the foundry. The output of the synthesisprocess is a gate-level netlist.Netlist• The netlist must undergo formal verification to prove that RTLand netlist are equivalent.Checks• Preliminary timing results after synthesis are analysed, criticalpaths are checked against the project performancerequirements. If needed, the RTL description, constraints orsynthesis options are modified, and the synthesis is repeated.
6. Design and LayoutLayout• Analogue•This often requires hand crafting of the layout ata transistor level to construct customisedanalogue functions .•The size and shape being dictated by the floorplan. These blocks can subsequently beinterconnected at the top level.•On completion of the blocks the circuits will beback-extracted and re-simulated in order toaccount for layout parasitics.• Digital•When timing constraints are finally met, thedesign proceeds to the layout, which consists offloor planning, placement and routing.• Some other important tasks are performed atthis step, including clock tree insertion.
7. Design and LayoutDRCand LVS• The last stage before tape out includes thefollowing checks:• DRC (design rule check) is a check that the layoutconforms to the foundry-specific rules.• LVS (layout versus schematic) is a formal equivalencecheck between the post-synthesis netlist and the finallayout.Tapeout• At last the resulting layout in GDSII format ishanded to the semiconductor fabrication plant(foundry).• This process is called tape out.
1. Wafer ProcessingThe Czochralski Process A typical wafer is made out of extremelypure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to300 mm (slightly less than 12 inches) indiameter using the Czochralski process. These ingots are then sliced into wafersabout 0.75 mm thick and polished toobtain a very regular and flat surface. Once the wafers are prepared, manyprocess steps are necessary to producethe desired semiconductor integratedcircuit. In general, the steps can begrouped into two major parts:Front-end-of-line (FEOL) processingBack-end-of-line (BEOL) processing
2. Wafer ProcessingDeposition Any process that grows, coats, orotherwise transfers a material ontothe wafer. Available technologies consist of Physical vapour deposition (PVD) Chemical vapour deposition (CVD) Electrochemical deposition (ECD) Molecular beam epitaxy (MBE) More recently, atomic layerdeposition (ALD) …among others.Removal processes Any that remove material from thewafer either in bulk or selectively andconsist primarily of etch processes,either wet etching or dry etching. Chemical-mechanical planarisation(CMP) is also a removal process usedbetween levels.
3. Wafer ProcessingPatterning The series of processes that shape or alter the existingshape of the deposited materials and is generally referredto as lithography. For example, in conventional lithography, the wafer iscoated with a chemical called a photoresist. Thephotoresist is exposed by a stepper, a machine thatfocuses, aligns, and moves the mask, exposing selectportions of the wafer to short wavelength light. The unexposed regions are washed away by a developersolution. After etching or other processing, the remainingphotoresist is removed by plasma ashing.Modification of electrical properties Historically consisted of doping transistor sources anddrains originally by diffusion furnaces and later by ionimplantation. These doping processes are followed by furnace annealor in advanced devices, by rapid thermal anneal (RTA)which serve to activate the implanted dopants. Modification of electrical properties now also extends toreduction of dielectric constant in low-k insulatingmaterials via exposure to ultraviolet light in UVprocessing (UVP).
4. Wafer ProcessingFEOLFEOL processing The formation of the transistors directly in the silicon. The raw wafer is engineered bythe growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performedto improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such assilicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystallattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of aninsulating layer between the raw silicon wafer and the thin layer of subsequent siliconepitaxy. This method results in the creation of transistors with reduced parasitic effects.Gate oxide and implants Front-end surface engineering is followed by: growth of the gate dielectric, traditionallysilicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions,and subsequent implantation or diffusion of dopants to obtain the desiredcomplementary electrical properties. In dynamic random access memory (DRAM) devices, storage capacitors are alsofabricated at this time, typically stacked above the access transistor.
5. Wafer ProcessingBEOLMetal Layers Once the various semiconductor deviceshave been created, they must beinterconnected to form the desiredelectrical circuits. This occurs in a series of wafer processingsteps collectively referred to as BEOL (notto be confused with back end of chipfabrication which refers to the packagingand testing stages). BEOL processing involves creating metalinterconnecting wires that are isolated bydielectric layers. The insulating material was traditionally aform of SiO2 or a silicate glass, but recentlynew low dielectric constant materials arebeing used. These dielectrics presently take the form ofSiOC and have dielectric constants around2.7 (compared to 3.9 for SiO2), althoughmaterials with constants as low as 2.2 arebeing offered to chipmakers.
6. Wafer ProcessingBEOLInterconnect Synthetic detail of a standard cell throughfour layers of planarized copperinterconnect, down to the polysilicon, wellsand substrate. More recently, as the number ofinterconnect levels for logic hassubstantially increased due to the largenumber of transistors that are nowinterconnected in a modern chip, thetiming delay in the wiring has becomesignificant prompting a change in wiringmaterial from aluminium to copper andfrom the silicon dioxides to newer low-Kmaterial. As the number of interconnect levelsincreases, planarization of the previouslayers is required to ensure a flat surfaceprior to subsequent lithography. Without it,the levels would become increasinglycrooked and extend outside the depth offocus of available lithography, interferingwith the ability to pattern.
7. Processing – PrototypingThere are two methods of prototyping;The first silicon MPW |MLMMulti Product Wafer (MPW) Shared silicon technology for theparallel processing of several deviceson one wafer Delivery of dies or ceramic samplesBenefits: Development chargessignificantly reducedDisadvantages: Fixed start dates and leadtimes Only a small number ofuntested samples available No volume production withthese masks
8. Processing – PrototypingThere are two methods of prototyping;The first silicon MPW |MLMMulti Level Mask (MLM) 4 mask levels drawn on the same reticule Mask costs reduced down to 1/4 for alltechnology nodesBenefits: Flexible tape-in dates Start-stop options and designrevisions possibleDisadvantages: No volume production withthese masks
9. ProcessingWafer ThinningWafer Thinning A semiconductor device fabrication stepduring which wafer thickness is reduced toallow for stacking and high densitypackaging of integrated circuits (IC). ICs are being produced on semiconductorwafers that undergo a multitude ofprocessing steps. The silicon waferspredominantly being used today havediameters of 20 and 30 cm. They areroughly 750 μm thick to ensure a minimumof mechanical stability and to avoid warpingduring high-temperature processing steps. The backside of the wafers are ground priorto wafer dicing (where the individualmicrochips are being singulated). Wafersthinned down to 75 to 50 μm are commontoday.The process is also known as ‘Backlap’ orWafer backgrinding‘.
10. ProcessingWafer DicingWafer Dicing The process by which die are separated from a waferof semiconductor following the processing of thewafer. The dicing process can be accomplished byscribing and breaking, by mechanical sawing(normally with a machine called a dicing saw) or bylaser cutting. Following the dicing process theindividual silicon chips are encapsulated into chipcarriers . During dicing, wafers are typically mounted on dicingtape which has a sticky backing that holds the waferon a thin sheet metal frame. Once a wafer has beendiced, the pieces left on the dicing tape are referredto as die, dice or dies. These will be packaged in asuitable package or placed directly on a printedcircuit board substrate as a "bare die". The area thathas been cut away are called die streets which aretypically about 75 micrometres (0.003 inch) wide. The die created may be any shape generated bystraight lines, but they are typically rectangular orsquare shaped.
1. PackagingDevelopmentEarly Flat PacksThe earliest integrated circuits were packaged in ceramic flat packs, which continued to be used by the militaryfor their reliability and small size for many years. Commercial circuit packaging quickly moved to the dual in-linepackage (DIP), first in ceramic and later in plasticPGA & LCCIn the 1980s pin counts of VLSI circuits exceeded the practical limit for DIP packaging, leading to pin grid array(PGA) and leadless chip carrier (LCC) packages. Surface mount packaging appeared in the early 1980s andbecame popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, asexemplified by small-outline integrated circuit — a carrier which occupies an area about 30 – 50% less than anequivalent DIP, with a typical thickness that is 70% less.This package has "gull wing" leads protruding from the two long sidesand a lead spacing of 0.050 inches.Small Outline Integrated CircuitsSmall-outline integrated circuit (SOIC) and Plastic leadedchip carrier (PLCC) packages. In the late 1990s,plastic quad flat pack (PQFP) and thin small-outline packages (TSOP)became the most common for high pin count devices,though PGA packages are still often used for high-end microprocessors.
2. PackagingBGD | SiPBall grid array (BGA) packages Have existed since the 1970s. Flip-chip BallGrid Array packages, which allow for muchhigher pin count than other package types,were developed in the 1990s. In an FCBGA package the die is mountedupside-down (flipped) and connects to thepackage balls via a package substrate that issimilar to a printed-circuit board ratherthan by wires. FCBGA packages allow an array of input-output signals (called Area-I/O) to bedistributed over the entire die rather thanbeing confined to the die periphery.System in a Package (SiP) When multiple dies are stacked in onepackage, it is called SiP, for System InPackage, or three-dimensional integratedcircuit. When multiple dies are combined on asmall substrate, often ceramic, its called anMCM, or Multi-Chip Module.
3. PackagingQFN Part 1QFN Flat no-leads packages such as QFN (quad-flatno-leads) and DFN (dual-flat no-leads)physically and electrically connect integratedcircuits to printed circuit boards. Flat no-leads,also known as MicroLead Frame, is a surface-mount technology, one of several packagetechnologies that connect ICs to the surfacesof PCBs without through-holes. Flat no-lead is a near chip scale packageplastic encapsulated package made with aplanar copper lead frame substrate.Perimeter lands on the package bottomprovide electrical connections to the PCB. Flat no-lead packages include an exposedthermal pad to improve heat transfer outof the IC (into the PCB). Heat transfer canbe further facilitated by metal vias in thethermal pad.The QFN package is similar to the quad-flatpackage, and a ball grid array.
4. PackagingQFN Part 2QFN packages Two types of QFN packages are common: air-cavity QFNs, with an air cavity designed intothe package, and plastic-moulded QFNs withair in the package minimized.Plastic Moulded QFN Less-expensive plastic-moulded QFNs usuallylimited to applications up to ~2–3 GHz. It is usually composed of just 2 parts, aplastic compound and copper lead frame,and does not come with a lid.Air-cavity QFN In contrast, the air-cavity QFN is usually madeup of 3 parts; a copper lead frame, plastic-moulded body (open, and not sealed), andeither a ceramic or plastic lid. It is usually more expensive due to itsconstruction, and can be used for microwaveapplications up to 20–25 GHz.QFN packages can have a single row of contacts or adouble row of contacts.
5. PackagingFlip ChipFlip chip | C4 Flip chip, also known as Controlled CollapseChip Connection or its acronym, C4, is amethod for interconnecting semiconductordevices, such as IC chips andMicroelectromechanical systems (MEMS),to external circuitry with solder bumps thathave been deposited onto the chip pads. The solder bumps are deposited on thechip pads on the top side of the waferduring the final wafer processing step. Inorder to mount the chip to externalcircuitry (e.g., a circuit board or anotherchip or wafer), it is flipped over so thatits top side faces down, and aligned sothat its pads align with matching pads onthe external circuit, and then the solderis flowed to complete the interconnect. This is in contrast to wire bonding, inwhich the chip is mounted upright andwires are used to interconnect the chippads to external circuitry.
6. PackagingFlip Chip ProcessMounted chip is “under-filled” using anelectrically-insulating adhesiveSolder balls are then re-melted (typically usinghot air reflow)Chips are flipped and positioned so that thesolder balls are facingthe connectors on the external circuitryChips are cutSolder dots are deposited on eachof the padsPads are metalized on the surfaceof the chipsIntegrated circuits are created on the wafer
ASIC Initial EvaluationJoint Evaluation Device evaluation is conducted by both theSWINDON design team and also the customer. The design team will evaluate the device as astand alone component and the customer willevaluate the device within it’s system. It is preferably conducted on identicalevaluation boards and set up in order to beable to accurately correlate results.Initial evaluation: - Power up. Turn on the power supply and check themains fuse has not blown, if not check currentconsumption in key modes. Check functionality either, optimistically,everything at once or block by block then afull functional test. Look at the performance aspects (accuracy,speed, settling time etc.) that are keyperformance aspects to the chip for a fewsamples at room temperature..
ASIC Full EvaluationFunctional and Parametric Once the initial checking has beencompleted then a full evaluation (functionaland parametric) against the specification isthen carried out. This is conducted over the environmentalwindow (temperature and voltage), over alimited number of samples (5 to 10), allaccording to the evaluation schedule. T his schedule should be in existence wellbefore the initial prototype chips arrive atthe respective companies.Parallel Testing In parallel samples will go to the testdepartment so that ATE development canproceed. This will need a large number of samples tobe tested to ensure that the functional andparametric yield is up to expectation.
ASIC Test DevelopmentPart 1The Test Development phaseConsists of developing the tests for the state of the artASICs. It is conducted in close co-operation with thedesign team to develop DFT strategies, test methods,verify test structures through simulation and generatetest vectors.This phase covers the following areas:1. Structural tests - Develop test vectors forATPG/JTAG/IDDQ.2. Memory Tests - Develop test vectors forembedded memories.3. Develop tools to support Failure analysisand Yield enhancement teams to physicallylocated failure locations on the chip.4. Mixed-signal tests - Develop test vectorsfor on-chip PLLs, DACs, ADCs, and otheranalog/RF blocks.5. Functional tests - Develop broadsidefunctional/Fmax test vectors for embeddedcontrollers and DSP cores.6. Behavioural Modelling - Develop analogmodels (DAC, ADC, PLL, up/downconverters and amplifiers) for pre-siliconverification and test vector generation.
ASIC Test DevelopmentPart 2Automatic Test Equipment (ATE ) The aim is for the implementation ofthese test vectors and methodologieson Automatic Test Equipment (ATE)during first silicon debug,characterization, and production. The required skills to perform thiscritical function includes; Strong knowledge of DFT: ATPG,JTAG, IDDQ, At-speed ATPG, faultsimulation, fault analysis. Knowledge of Iddq testtechniques and At-speed ATPGincluding transition and path delay Strong knowledge of test benchdevelopment, simulation debug,behavioural model development.
ASIC Test DevelopmentResultsBespoke Test RegimeThe results of this work in a bespoke testregime for the ASIC under test andincludes; Fully automated waferand package level test Fully automated, onlinetest and QA procedures 100% wafer level test,each device 100% package level test,each package Real-time yield statistics Wafer and package leveltests correlated 100% Datalog, each device Tri temperature test PPM field failure rate sub 1ppm
ASIC ProductionThe production of the ASIC comprisesmany aspects of are that have already been covered.1. Production Acceptance Review Prototypes are reviewed forProduction Suitability2. Wafer Fabrication Production Orders from SiliconFabricator3. Wafer Probe Die are tested at wafer level at CSS Test Program is Custom Made foryour ASIC Key Product Characteristics (KPCs)are collected for Statistical ProcessControl4. Packaging A wide variety of packages areavailable, as well as die delivery5. Package Testing Packages are typically tested at CSS Test Program is Custom Made Delivery in rails, tape & reel orwaffle packs (die)6. Production Reports Probe and Package Test Data isanalysed by Quality Engineeringand Yield and Statistical Process Controlinformation is available to ASICcustomers.7. Order Fulfilment and LogisticsForecasting Supply Chain Management Support functions
It is hugely preferential if your ASIC supplier has many of the fulfilment and logisticscapabilities in house. This will provide a much more risk averse supply chain andSWINDON offers the complete service. From forecasting to shipping…ForecastingSupply ChainManagement ManufacturingWarehousing/ ShippingOrderManagementFulfilment and LogisticsIn-house capabilities
The support functions that your ASIC supplier provides can be critical in order for yourcompany to perform to its highest level. SWINDON offers the highest support….EnvironmentalHealth and SafetyWarranty andReturnsFinancialsResourceManagementOperationsSupportFulfilment and LogisticsSupport Functions
10 Reasons why…SWINDON makes a good choicefor your next ASIC projectDesign and productionisation expertiseGained over 30 years of successful projectsFixed development costs and unit pricesDesign ownershipProduction supplyIn house wafer probe and ATE production testLifetime product supportFinancial stabilityQualityPartnership Approach
Any questions? We have a full range of resources from case histories toplanning checklists Please visit our web site www.swindonsilicon.co.ukHeadquarters & Design CentreSwindon Silicon Systems LimitedRadnor StreetSwindon Wiltshire SN1 3PRUnited KingdomTel: +44 (0) 1793 649400email: firstname.lastname@example.org