4.Draw the circuit for 3-to-8 line decoder.3-to-8 DecoderA 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of which is shownbelow.Truth TableX Y Z F0 F1 F2 F3 F4 F5 F6 F70 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1SymbolFrom the truth table we can draw the circuit diagram as shown in figure below.
Circuit for 3 to 8 line decoder.4.Explain the working of the modems?As we know that the computers can’t understand our language. Computers understand the language of 0’sand 1’s i.e. digital form. The modem will modulate the signal into a sine wave. So, this modulated digitalsignal can easily run over the telephone lines. Then the signal will reach the IP hub. After this thedemodulation of the signal will take place into digital form. Then you will be connected to the internet. Allthese processes are performed by modem at extremely high speeds. The speed of the modem depends uponthe number of the available access lines and the technology of the modem.Today’s the modems are of very high speeds. But some people are still using the slow speed modemshaving speed nearly 56kbps.The features of modem are discussed below:
1. The speed of the modem is measured in bps means bits per second. Data transfer speed can be increasedby using the technique of data compression.2. If we are using a modem having auto answering facility. Then our modem will be able to attend callseven in our absence.3. Modems work basically in two modes. One is voice mode and other is data mode. In voice mode modemacts like a simple telephone. But in data mode modem acts as a Simple modem. These types of modemshave a switch which is helpful in changing the mode i.e. from voice mode to data mode and from datamode to voice mode. For voice communication, loudspeaker and a microphone is implemented in themodem.4. Some modems have the ability to compress data. These modems compress data before sending toimprove the data transfer rates. But there must be a similar technology modem to decompress the data atthe receiver end.5. There are basically three types of modems. All the three types are discussed in detail below:a) External Modemsb) Internal Modemsc) PCMCIA ModemExternal Modems: A serial cable connection is needed to connect an external modem to a PC. Thesemodems use their own power supplies. These modems have their independent controls.Internal Modems: Internal modems are basically integrated on a chip. These are put up into the PCI slotsof the computer. There is no need of any external power supply for internal modems. These modems usethe power supply of the PC. Their installation in PC is quite very simple.3.Write a short note on ADC. Ans:An analog-to-digital converter is an electronic integrated circuit, which converterscontinuoussignals to discrete digital numbers. The reverse operation is performed by a digital-to-analogconverter.Typically, an adc is an electronic device that converter an input analog voltage to a digitalnumber. The digital output may be using different coding schemes, such as binary, gray code ortwo’s complement binary. However, some non electronic or only partially electronic devices, suchas rotary encoders, can also be considered ADCs. Resolution can also be defined electrically,and expressed in volts. The voltage resolution ofan ADC is equal to it’s over all voltagemeasurement range divided by the number of discrete intervals as in the formula:Where:Q is resolution in volts per step (volts per output code).EFSR is the fu scale voltage = VRefHi – Vreflo and M is the ADC’s resolution in bits.The number of intervals is given by the number of available levels (output code),Which is: N = 2M.
Some example may help:Example 1:Full scale measurement range = 0 to 10 volts.ADC resolution is 12 bits: 212 = 4096 quantization level (codes)ADC voltage resolution is: (10V – 0V) / 4096 codes = 10V / 4096 codes 0.00244 volts/code2.44mV/code.9. Write a short note on Digital Versatile Disk.DVD is also known as Digital Versatile Disk or Digital video disc, is an opticaldisc storage media format, invented and developed by Philips, Sony, Toshiba,and Panasonic in 1995. DVDs offer higher storage capacity than compact discs whilehaving the same dimensions.Pre-recorded DVDs are mass-produced using molding machines that physically stampdata onto the DVD. Such discs are known as DVD-ROM, because data can only be readand not written nor erased. Blank recordable DVDs (DVD-R and DVD+R) can berecorded once using a DVD recorderand then function as a DVD-ROM. RewritableDVDs (DVD-RW, DVD+RW, and DVD-RAM) can be recorded and erased multiple times.DVDs are used in DVD-Video consumer digital video format and in DVD-Audio consumer digital audio format, as well as for authoring AVCHD discs. DVDscontaining other types of information may be referred to as DVD data discs.In 1993, two optical disc storage formats were being developed. One was theMultimedia Compact Disc (MMCD), backed by Philips and Sony, and the other was theSuper Density (SD) disc, supported by Toshiba, Time Warner, MatsushitaElectric, Hitachi, Mitsubishi Electric, Pioneer, Thomson, and JVC.Representatives of the SD camp approached IBM, asking for advice on the file system touse for their disc as well as seeking support for their format for storing computerdata. Alan E. Bell, a researcher from IBMs Almaden Research Center got that requestand also learned of the MMCD development project. Wary of being caught in a repeat ofthe costly videotape format war between VHSand Betamax in the 1980s, he convened agroup of computer industry experts, including representativesfrom Apple, Microsoft, Sun, Dell, and many others. This group was referred to as theTechnical Working Group, or TWG.
The TWG voted to boycott both formats unless the two camps agreed on a single,converged standard. Lou Gerstner, president of IBM, was recruited to apply pressureon the executives of the warring factions. Eventually, the computer companies won theday, and a single format, now called DVD, was agreed upon. The TWG alsocollaborated with the Optical Storage Technology Association(OSTA) on the use of theirimplementation of the ISO-13346 file system (known as Universal Disc Format) for useon the new DVDs.Philips and Sony decided it was in their best interest to avoid another format war overtheir Multimedia Compact Disc, and agreed to unify with companies backing the SuperDensity Disc to release a single format with technologies from both. The specificationwas mostly similar to Toshiba and Matsushitas Super Density Disc, except for the dual-layer option (MMCD was single-sided and optionally dual-layer, whereas SD was single-layer but optionally double-sided) and EFMPlus modulation.EFMPlus was chosen because of its great resilience to disc damage, such as scratchesand fingerprints. EFMPlus, created by Kees Immink (who also designed EFM), is 6%less efficient than the modulation technique originally used by Toshiba, which resulted ina capacity of 4.7 GB, as opposed to the original 5 GB. The result was the DVDspecification, finalized for the DVD movie player and DVD-ROM computer applications inDecember 1995.The DVD Video format was first introduced by Toshiba in Japan in November 1996, inthe United States in March 1997 (test marketed), in Europe in October 1998, and inAustralia in February 1999.In May 1997, the DVD Consortium was replaced by the DVD Forum, which is open to allother companies10.Write a note on DAC types.In electronics, a digital-to-analog converter (DAC or D-to-A) is a device that convertsa digital (usually binary) code to an analog signal (current, voltage, orelectric charge).An analog-to-digital converter (ADC) performs the reverse operation.DAC types
The most common types of electronic DACs are:The pulse-width modulator, the simplest DAC type. A stable current or voltage is switchedinto a low-pass analog filter with a duration determined by the digital input code. This technique isoften used for electric motor speed control, but has many other applications as well.Oversampling DACs or interpolating DACs such as the delta-sigma DAC, use a pulse densityconversion technique. The oversampling technique allows for the use of a lower resolution DACinternally. A simple 1-bit DAC is often chosen because the oversampled result is inherently linear.The DAC is driven with a pulse-density modulated signal, created with the use of a low-passfilter,step nonlinearity (the actual 1-bit DAC), and negative feedback loop, in a techniquecalled delta-sigma modulation. This results in an effective high-pass filter acting onthe quantization (signal processing) noise, thus steering this noise out of the low frequencies ofinterest into the megahertz frequencies of little interest, which is called noise shaping. Thequantization noise at these high frequencies is removed or greatly attenuated by use of an analoglow-pass filter at the output (sometimes a simple RC low-pass circuit is sufficient). Most very highresolution DACs (greater than 16 bits) are of this type due to its high linearity and low cost. Higheroversampling rates can relax the specifications of the output low-pass filter and enable furthersuppression of quantization noise. Speeds of greater than 100 thousand samples per second (forexample, 192 kHz) and resolutions of 24 bits are attainable with delta-sigma DACs. A shortcomparison with pulse-width modulationshows that a 1-bit DAC with a simple first-order integrator would have to run at 3 THz (which is physically unrealizable) to achieve 24meaningful bits of resolution, requiring a higher-order low-pass filter in the noise-shaping loop. Asingle integrator is a low-pass filter with a frequency response inversely proportional to frequencyand using one such integrator in the noise-shaping loop is a first order delta-sigma modulator.Multiple higher order topologies (such as MASH) are used to achieve higher degrees of noise-shaping with a stable topology.The binary-weighted DAC, which contains one resistor or current source for each bit of the DACconnected to a summing point. These precise voltages or currents sum to the correct outputvalue. This is one of the fastest conversion methods but suffers from poor accuracy because ofthe high precision required for each individual voltage or current. Such high-precision resistorsand current sources are expensive, so this type of converter is usually limited to 8-bit resolution orless.The R-2R ladder DAC which is a binary-weighted DAC that uses a repeating cascaded structureof resistor values R and 2R. This improves the precision due to the relative ease of producingequal valued-matched resistors (or current sources). However, wide converters perform slowlydue to increasingly large RC-constants for each added R-2R link.The thermometer-coded DAC, which contains an equal resistor or current-source segment foreach possible value of DAC output. An 8-bit thermometer DAC would have 255 segments, and a16-bit thermometer DAC would have 65,535 segments. This is perhaps the fastest and highestprecision DAC architecture but at the expense of high cost. Conversion speeds of >1 billionsamples per second have been reached with this type of DAC.Hybrid DACs, which use a combination of the above techniques in a single converter. Most DACintegrated circuits are of this type due to the difficulty of getting low cost, high speed and highprecision in one device.The segmented DAC, which combines the thermometer-coded principle for the most significantbits and the binary-weighted principle for the least significant bits. In this way, a compromise isobtained between precision (by the use of the thermometer-coded principle) and number of
resistors or current sources (by the use of the binary-weighted principle). The full binary-weighteddesign means 0% segmentation, the full thermometer-coded design means 100% segmentation.3.Explain temperature and weather forecast system with a neat circuit diagram.Assumptions/Design Criteria:♦ The barometer will be operated indoors. This will minimize output variations causedby temperature and will lengthen the calibration intervals. It also means the circuitboard will not have to be weatherproofed.♦ Will be easy to calibrate. This means there will be a maximum of 1 calibrationadjustment.♦ The operating range will be from 28.00 inHg to 32.00 inHg♦ Resolution will be greater than .01 inHg from sea level to 10,000 feet.♦ The interface will be standard Dallas Semiconductor 1-wire.♦ Because the unit will be designed for indoor operation, it can be externally powered.♦ Will utilize the Motorola MPX4115A pressure transducer.Based on these assumptions, table 1 was generated. This table calculates the stationpressure for both the minimum (28.00) and the maximum (32.00) pressures for altitudesfrom sea level to 10,000 feet in 1000 foot increments. The station pressure is thenconverted to MPX4115A pressure sensor volts. Looking at the table, I discovered thepredominant change in altitude in the offset voltage of the pressure sensor. I decidedthat this will be the adjustable parameter, and that the circuit gain would be fixed.The OA Offset column is the op amp offset voltage that compensates for altitude. Thiswill be the only calibration variable. Since the instrumentation amplifier is a rail-to-raildevice, in theory it will operate down to 0 volts. However, to provide some margin, theoffsets were chosen to allow a minimum of .2 volts at the lowest pressure. The gain of10 was chosen to allow maximum output voltage swing for all altitudes. The resulting op
amp output voltages are listed in OA Output c column. This is the voltage applied to theDS2438 Vad input.Circuit Design:The following circuit design satisfies these requirements. I selected the INA122instrumentation amp for several reasons: it eliminated several external resistors and itprovides a very stable gain over a wide temperature. It also provides excellent rail-to-railoperation allowing full use of the 10 volt input range of the DS2438. The 40.2K ohmresistor sets the gain to 10. The variable resistor allows adjustment of the offset voltagefrom 2.0v to 4.0v. All parts are available from Digikey except thepressure sensor, which is available from Newark.
Calibration:Hardware calibration is simply a matter of setting the offset voltage to the value listed intable 1 for your altitude. A jumper on the input of the DS2438 allows the use of theDS2438 to measure the offset. Put the jumper in the A-C position and using the iButtonViewer for the DS2438, set the voltage to the table value using the 25-turn pot. Once it’sset, put the jumper in the A-B position to read pressure.For altitudes in between the valueslisted in the table, simple interpolation will giveaccurate results. An Excel spreadsheet will be also available online to calculateintermediate values.Software:
Routines currently exist to measure the DS2438s Vad voltage. Once this voltage ismeasured, the pressure is calculated using:Press = slope * Vad + interceptWhere the slope and intercept are the values listed in table 1 for your altitude. Theprototype code I used had an external text file to store the slope and intercept values.This allows the user to edit the file to fine-tune the calibration if desired.Fine-tuning can be accomplished by monitoring the pressure and comparing it with aknown reference source, such as a nearby airport or NOAA weather. Start by adjustingthe intercept. When the reference station indicates a pressure near mid-scale (30.00inHg), adjust the software intercept value until your weather station matches. Nowmonitor the pressure extremes to determine if the slope needs adjustment. An Excelspreadsheet will be available as an aid.Future Options:A fixed resistor could replace the variable resistor. This would eliminate any hardwareadjustments. The value would have to be calculated for a given altitude. Anotherpossibility is to use several DS2406 1-wire switches or a programmable potentiometerto set the offset programmatically10. Draw and explain the working of JK, S-R, and D flip flops.Answer:- Each flip-flop stores a single bit of data, which is emittedthrough the Q output on the east side. Normally, the value can becontrolled via the inputs to the west side. In particular, the valuechanges when the clock input, marked by a triangle on each flip-flop,rises from 0 to1; on this rising edge, the value changes according tothe corresponding table below.D Flip-Flop J-K Flip-Flop S-R Flip-Flop
Another way of describing the different behavior of the flip-flops is inEnglish text. • D Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop becomes the value of the D input (Data) at that instant. • J-K Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop toggles if the J and K inputs are both 1, remains the same if they are both 0, and changes to the K input value if J and K are not equal. (The names J and K do not stand for anything.) • R-S Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop remains unchanged if R and S are both 0, becomes 0 if the R input (Reset) is 1, and becomes 1 if the S input (Set) is 1. The behavior in unspecified if both inputs are 1. (In Logisim, the value in the flip-flop remains unchanged.)6. Draw and explain the operation of parallel-in-parallel-out shift register.
The purpose of the parallel-in/ parallel-out shift register is to take in paralleldata, shift it, then output it as shown below. A universal shift register is a do-everything device in addition to the parallel-in/ parallel-out function.Above we apply four bit of data to a parallel-in/ parallel-out shift registerat DA DB DC DD. The mode control, which may be multiple inputs, controlsparallel loading vs shifting. The mode control may also control the directionof shifting in some real devices. The data will be shifted one bit position foreach clock pulse. The shifted data is available at the outputs QA QB QC QD .The "data in" and "data out" are provided for cascading of multiple stages.Though, above, we can only cascade data for right shifting. We couldaccommodate cascading of left-shift data by adding a pair of left pointingsignals, "data in" and "data out", above.The internal details of a right shifting parallel-in/ parallel-out shift registerare shown below. The tri-state buffers are not strictly necessary to theparallel-in/ parallel-out shift register, but are part of the real-world deviceshown below.
The 74LS395 so closely matches our concept of a hypothetical right shiftingparallel-in/ parallel-out shift register that we use an overly simplified versionof the data sheet details above. See the link to the full data sheet more moredetails, later in this chapter.LD/SH controls the AND-OR multiplexer at the data input to the FFs. If LD/SH=1, the upper four AND gates are enabled allowing application of parallelinputs DA DB DC DD to the four FF data inputs. Note the inverter bubble at theclock input of the four FFs. This indicates that the 74LS395 clocks data onthe negative going clock, which is the high to low transition. The four bits ofdata will be clocked in parallel from DA DB DC DD to QA QB QC QD at the nextnegative going clock. In this "real part", OC must be low if the data needs tobe available at the actual output pins as opposed to only on the internal FFs.The previously loaded data may be shifted right by one bit positionif LD/SH=0 for the succeeding negative going clock edges. Four clockswould shift the data entirely out of our 4-bit shift register. The data would belost unless our device was cascaded from QD to SER of another device.
Above, a data pattern is presented to inputs DA DB DC DD. The pattern isloaded to QA QB QC QD . Then it is shifted one bit to the right. The incomingdata is indicated by X, meaning the we do no know what it is. If the input(SER) were grounded, for example, we would know what data (0) wasshifted in. Also shown, is right shifting by two positions, requiring two clocks.The above figure serves as a reference for the hardware involved in rightshifting of data. It is too simple to even bother with this figure, except forcomparison to more complex figures to follow.
Right shifting of data is provided above for reference to the previous rightshifter.If we need to shift left, the FFs need to be rewired. Compare to the previousright shifter. Also, SI and SO have been reversed. SI shifts to QC. QC shiftstoQB. QB shifts to QA. QA leaves on the SO connection, where it couldcascade to another shifter SI. This left shift sequence is backwards from theright shift sequence.Above we shift the same data pattern left by one bit.There is one problem with the "shift left" figure above. There is no market forit. Nobody manufactures a shift-left part. A "real device" which shifts onedirection can be wired externally to shift the other direction. Or, should wesay there is no left or right in the context of a device which shifts in only onedirection. However, there is a market for a device which will shift left or right
on command by a control line. Of course, left and right are valid in thatcontext.What we have above is a hypothetical shift register capable of shifting eitherdirection under the control of L/R. It is setup with L/R=1 to shift thenormal direction, right. L/R=1 enables the multiplexer AND gates labeled R.This allows data to follow the path illustrated by the arrows, when a clock isapplied. The connection path is the same as the"too simple" "shift right"figure above.Data shifts in at SR, to QA, to QB, to QC, where it leaves at SR cascade. Thispin could drive SR of another device to the right.5. Write a short note on J-K Master Slave Flip-Flop.
The Master-Slave JK Flip-FlopThe input signals J and K are connected to the gated "master" SR flip-flop which "locks" the inputcondition while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of the "slave"flip-flop is the inverse (complement) of the "master" clock input, the "slave" SR flip-flop does nottoggle. The outputs from the "master" flip-flop are only "seen" by the gated "slave" flip-flop whenthe clock input goes "LOW" to logic level "0". When the clock is "LOW", the outputs from the"master" flip-flop are latched and any additional changes to its inputs are ignored. The gated"slave" flip-flop now responds to the state of its inputs passed over by the "master" section. Thenon the "Low-to-High" transition of the clock pulse the inputs of the "master" flip-flop are fedthrough to the gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the sameinputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered.Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to theoutput on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a"Synchronous" device as it only passes data with the timing of the clock signal.7. List the fundamental logical gates.Ans:The seven fundamental logic gates are:1. NOT (Inverter)2. AND3. NAND4. OR5. NOR6. XOR7. XNOR8. Explain two way switches.
Ans: A switch is a mechanical device used to connect and disconnect a circuit at will.Switches cover a wide range of types, from subminiature up to industrial plant switchingmegawatts of power on high voltage distribution lines.In applications where multiple switching options are required (e.g., a telephone service),mechanical switches have long been replaced by electronic switching devices which canbe automated and intelligently controlled.The switch is referred to as a "gate" when abstracted to mathematical form. Inthe philosophy of logic, operational arguments are represented as logicgates.The use of electronic gates to function as a system of logical gates is thefundamental basis for the computer –i.e A computer is a system of electronicswitches which function as logic gates.There are tactical switches.major scale is inches.A railroad switch is not electrical, but a mechanical device to divert a train from one trackto another.In the simplest case, a switch has two pieces of metal called contacts that touch to makea circuit, and separate to break the circuit. The contact material is chosen for itsresistance to corrosion, because most metals form insulating oxides that would preventthe switch from working. Contact materials are also chosen on the basis of electricalconductivity, hardness (resistance to abrasive wear), mechanical strength, low cost andlow toxicity.Sometimes the contacts are plated with noble metals. They may be designed to wipeagainst each other to clean off any contamination. Nonmetallic conductors, such asconductive plastic, are sometimes used.ActuatorThe moving part that applies the operating force to the contacts is calledthe actuator, and may be a toggle or dolly, a rocker, a push-button, or any type ofmechanical linkage.Contact arrangementsTriple Pole Single Throw (TPST or 3PST) knife switch used to short the windings of a 3phase wind turbine for braking purposes. Here the switch is shown in the open position.A pair of contacts is said to be "closed" when there is no space between them,allowing electricity to flow from one to the other. When the contacts are separated by aninsulating air gap, an air space, they are said to be "open," and no electricity can flow attypical voltages.
Switches can be and are classified according to the arrangement of their contacts inelectronics fields—but electricians in the electrical wiring service business and theirelectrical supplier industries use different nomenclature, such as "one-way," "two-way,""three-way," and "four-way" switches—which have different meanings in North Americanand British cultural regions as is delineated in the table below.Some contacts are normally open (Abbreviated "n.o." or "no") until closed by operationof the switch, while others are normally closed ("n.c." or "nc") and opened by the switchaction, where the abbreviations given are commonly used on electronics diagrams forclarity of operation in assembly, analysis, or troubleshooting. The serve to synchronizemeaning with possible mistakes in wiring assembly, where wiring part of switch one wayand part another (usually opposite) way will pretty much guarantee things wont work asdesigned.A switch with both types of contact is called a changeover switch or "make-before-break"switch contact, whereas most switches have a spring-loaded action that momentarilydisconnect the load and so are "break-before-make" types. The type of switch usedcould be important, if for example, the switch selects two different power sources insteadof switching circuit loads, or the circuit load will not and cannot tolerate any interruptionin applied power.The terms pole and throw are also used to describe switch contact variations. A pole is aset of contacts, the switchs electrical terminals that are connected to and belong to asingle circuit, usually a load. A throw is one of two or more positions (the nomenclatureis also applied to rotary switches, which can have many throw positions) that the switchcan adopt, which normally, but not always correspond to the number positions the switchhandle or rotor can take when connecting between the common lead of the switch and apole or poles. A throw position which connects no terminals (poles), has a mismatchbetween positions and positions which connect terminals, but are quite useful to turnthings "Off" or for example, alternatively select between two scaled modes of operation.(For example, Bright illumination, moderate illumination, no illumination.)Switching a load on or off from two locations (for instance, turning a light on or off fromeither end of a flight of stairs) requires two SPDT switches. There are two basic methodsof wiring to achieve this, and another not recommended.In the first method, mains is fed into the common terminal of one of the switches; theswitches are then connected through the L1 and L2 terminals (swapping the L1 and L2terminals will just make the switches work the other way round), and finally a feed to the
light is taken from the common of the second switch. A connects to B or C, D connectsto B or C; the light is on if A connects to D, that is, if A and D both connect to B or bothconnect to C.The second method is to join the three terminals of one switch to the correspondingterminals on the other switch and take the incoming supply and the wire out to the lightto the L1 and L2 terminals. Through one switch A connects to B or C, through the otheralso to B or C; the light is on if B connects to C; that is, if A connects to B with one switchand to C with the other.Wiring needed in addition to the mains network (not including protective earths):First method: Double wire between both switches Single wire from one switch to the mains Single wire from the other switch to the load Single wire from the load to the mainsSecond method: Triple wire between both switches Single wire from any position between the two switches, to the mains Single wire from any position between the two switches, to the load Single wire from the load to the mainsIf the mains and the load are connected to the system of switches at one of them, then inboth methods we need three wires between the two switches. In the first method one ofthe three wires just has to pass through the switch, which tends to be less convenientthan being connected. When multiple wires come to a terminal they can often all be putdirectly in the terminal. When wires need to be joined without going to a terminal acrimped joint, piece of terminal block, wire nut or similar device must be used and thebulk of this may require use of a deeper back box.7. Design the counter that goes through states 0,1,2,4,0…using D flip-flops.
6. Convert the following decimal numbers to base 2:A.122Ans: 1111010B.98Ans: 11000101. Convert the following binary numbers to base 10.a. 10101101Ans:173b. 110110.1Ans:54.5