VSK Embedded Processing Video Lab

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VSK Embedded Processing Video Lab

  1. 1. Impulse Embedded Processing Video Lab ISE™ Design Suite Generate FPGA hardware Generate hardware interfaces HDL files FPGA bitmap C language software Compile and optimize
  2. 2. Workshop Agenda <ul><li>Step-By-Step Creation of a Streaming Video Application: </li></ul><ul><ul><li>You will learn how to: </li></ul></ul><ul><ul><ul><li>Use Xilinx reference hardware and software for fast development </li></ul></ul></ul><ul><ul><ul><li>Combine multiple streaming video filters in a single application </li></ul></ul></ul><ul><ul><ul><li>Use Xilinx Platform Studio (XPS) for system integration </li></ul></ul></ul><ul><ul><ul><li>Use an embedded MicroBlaze processor for video control </li></ul></ul></ul><ul><ul><ul><li>Combine multiple methods of design into a single project </li></ul></ul></ul><ul><ul><li>Steps: </li></ul></ul><ul><ul><ul><li>Start with a ready-to-use video reference design </li></ul></ul></ul><ul><ul><ul><li>Add a custom object detection and highlighting filter to the video stream </li></ul></ul></ul><ul><ul><ul><li>Control and configure the filter using an embedded MicroBlaze processor </li></ul></ul></ul><ul><ul><ul><li>Rebuild the project and test the enhanced video processing design </li></ul></ul></ul>Page
  3. 3. Video Design Overview Page DVI DVI The MicroBlaze processor will be used to dynamically configure filters Filter control (UART) Processor Local Bus (PLB) Custom C-language filter DVI In Gamma In 2D FIR Filter Gamma Out DVI Out Xilinx MicroBlaze Processor Fish Finder Filter
  4. 4. Video Starter Kit Hardware Page
  5. 5. Test the Pass-through Example Using Flash <ul><li>Setup the Video Components </li></ul><ul><ul><li>720p resolution video source  </li></ul></ul><ul><ul><ul><li>TViX player, laptop computer or other DVI/HDMI source </li></ul></ul></ul><ul><ul><li>Xilinx Video Starter Kit </li></ul></ul><ul><ul><ul><li>Spartan 3 Edition used for this workshop </li></ul></ul></ul><ul><ul><li>Video monitor </li></ul></ul><ul><ul><ul><li>Supporting 1280 x 720 resolution </li></ul></ul></ul><ul><li>Power Up and test the Video </li></ul><ul><ul><li>Start video source (“play”) </li></ul></ul><ul><ul><li>Xilinx reference designs will boot from Flash card </li></ul></ul><ul><ul><li>Press center push-button to load the DVI pass-through example </li></ul></ul><ul><ul><li>Verify video is displayed on monitor </li></ul></ul>Page
  6. 6. Load Project_2_Passthrough_Completed Page Xilinx Platform Studio™ Project Information Area Console Window System Assembly View
  7. 7. Test the Pass-Through Example Page 1 2
  8. 8. Examining the Impulse C Code Page The Impulse C-to-FPGA compiler generates parallel FPGA hardware from sequential software… C-language in, HDL out! The compiler also generates hardware interfaces such as DVI for video and PLB for processor I/O Compiler “export” scripts are used to generate auxiliary files as needed by Xilinx ISE Design Suite DVI DVI ISE™ Design Suite Generate FPGA hardware Generate hardware interfaces HDL files FPGA bitmap C language software Compile and optimize
  9. 9. Open the Fish Finder Impulse C Project Page
  10. 10. Fish Finder C-Code Design Review Page The Fish Finder algorithm is described using a C-language subroutine with streaming I/O interfaces…
  11. 11. Fish Finder C-Code Design Review Page Video I/O is described using Impulse C types and functions: Fish Finder Filter
  12. 12. Fish Finder C-Code Design Review Page DVI streaming video is represented as 27-bit integer data (24-bits of color, vsync, hsync and de): Unpacking a 27-bit video pixel and looking for start-of-frame… Packing and writing a filtered pixel… Fish Finder Filter
  13. 13. Fish Finder C-Code Design Review Page Loop pipelining and pipeline stage depth are easily specified using two pragmas in the C code… Automatic parallelizing of C statements enables complex, real-time processing of video signals.
  14. 14. Fish Finder C-Code Design Review Page These C statements create a spotlight effect, using simple geometry to calculate the radius:
  15. 15. Fish Finder Software Simulation Page Software simulation of a single frame…
  16. 16. Fish Finder Hardware Generation Page <ul><li>Choose a Platform Support Package (Xilinx DVI Video with PLB) </li></ul><ul><li>Specify an export directory </li></ul><ul><li>Generate hardware </li></ul><ul><li>Export hardware and software </li></ul>
  17. 17. Fish Finder Hardware Optimization Page Interactive pipeline optimization and analysis helps to quickly converge on the right solution for high-throughput video: The dataflow graph shows how the C- language statements were automatically parallelized by the compiler. The pipelining rate is critical for processing video signals at pixel-rate. A rate of 1 means a perfect video pipeline. Max Unit Delay helps you to understand and control timing and clock rates.
  18. 18. Add Fish Finder Filter to the EDK Project Page After generating and exporting the hardware from the Impulse environment, we can important into Platform Studio as a pcore:
  19. 19. Connect Fish Finder Filter to PLB and DVI Page
  20. 20. Connect Clocks and Reset Page
  21. 21. Generate Addresses Page Note: addresses generated may be different than shown above
  22. 22. Modify the Software Application Page We will modify the software application to add in the new Fish Finder menu and add the related filter control code.
  23. 23. Modify the Software Application Page Remove the leading comment characters (//) This change will enable the new menu feature:
  24. 24. Fish Finder C-Code Design Review Page Communication between MicroBlaze and Fish Finder is described using Impulse C co_stream API functions: Writing a configuration word from the MicroBlaze application… Polling to read the configuration word in the hardware process…
  25. 25. Add New Sources and Headers Page
  26. 26. Add New Sources and Headers Page
  27. 27. Build the Software Application Page
  28. 28. Test the Fish Finder Page 1 2
  29. 29. For Additional Information Page www.xilinx.com/vsk_s3 www.ImpulseC.com/Tutorials/Xilinx/VSK_S3

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