8086 architecture

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8086 architecture

  1. 1. 8086/8088 MicroprocessorIntroduction to the processor and its pin configuration
  2. 2. Topics• Basic Features• Pinout Diagram• Minimum and Maximum modes• Description of the pins
  3. 3. Basic Features• 8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus• 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus• Both manufactured using High-performance Metal Oxide Semiconductor (HMOS) technology• Both contain about 29000 transistors• Both are packaged in 40 pin dual-in-line package (DIP)
  4. 4. 8086/8088 Pinout DiagramsGND 1 40 VCC GND 1 40 VCCAD14 2 39 AD15 A14 2 39 A15AD13 3 38 A16/S3 A13 3 38 A16/S3AD12 4 37 A17/S4 A12 4 37 A17/S4AD11 5 36 A18/S5 A11 5 36 A18/S5AD10 6 35 A19/S6 A10 6 35 A19/S6AD9 7 34 BHE/S7 A9 7 34 SS0AD8 8 33 MN/MX A8 8 33 MN/MXAD7AD6 9 10 8086 32 31 RD HOLD AD7 AD6 9 10 8088 32 31 RD HOLDAD5 11 30 HLDA AD5 11 30 HLDAAD4 12 29 WR AD4 12 29 WRAD3 13 28 M/IO AD3 13 28 IO/MAD2 14 27 DT/R AD2 14 27 DT/RAD1 15 26 DEN AD1 15 26 DENAD0 16 25 ALE AD0 16 25 ALENMI 17 24 INTA NMI 17 24 INTAINTR 18 23 TEST INTR 18 23 TESTCLK 19 22 READY CLK 19 22 READYGND 20 21 RESET GND 20 21 RESET BHE has no meaning on the 8088 and has been eliminated
  5. 5. Multiplex of Data and Address Lines in 8088• Address lines A0-A7 and Data lines D0-D7 are GND 1 40 VCC A14 2 39 A15 A13 3 38 A16/S3 multiplexed in 8088. A12 4 37 A17/S4 A11 5 36 A18/S5 A10 6 35 A19/S6 These lines are labelled as A9 A8 AD7 7 8 9 8088 34 33 32 SS0 MN/MX RD AD0-AD7. AD6 AD5 AD4 10 11 12 31 30 29 HOLD HLDA WR – By multiplexed we mean AD3 AD2 AD1 13 14 15 28 27 26 IO/M DT/R DEN that the same pysical pin AD0 NMI 16 17 25 24 ALE INTA carries an address bit at INTR 18 23 TEST CLK 19 22 READY GND 20 21 RESET one time and the data bit another time
  6. 6. Multiplex of Data and Address Lines in 8086• Address lines A0-A15 and Data lines D0-D15 are multiplexed in 8086. These lines are labelled as AD0-AD15. GND 1 40 VCC AD14 2 39 AD15 AD13 3 38 A16/S3 AD12 4 37 A17/S4 AD11 5 36 A18/S5 AD10 6 35 A19/S6 AD9 7 34 BHE/S7 AD8 8 33 MN/MX AD7 AD6 9 10 8086 32 31 RD HOLD AD5 11 30 HLDA AD4 12 29 WR AD3 13 28 M/IO AD2 14 27 DT/R AD1 15 26 DEN AD0 16 25 ALE NMI 17 24 INTA INTR 18 23 TEST CLK 19 22 READY GND 20 21 RESET
  7. 7. Minimum-mode and Maximum-mode Systems• 8088 and 8086 microprocessors can be configured to work in either of the two modes: the minimum mode and the GND 1 40 VCC maximum mode AD14 AD13 2 3 39 38 AD15 A16/S3 AD12 4 37 A17/S4 Minimum mode: AD11 AD10 5 6 36 35 A18/S5 A19/S6  Pull MN/MX to logic 1 AD9 AD8 7 8 34 33 BHE/S7 MN/MX  Typically smaller systems and contains a AD7 AD6 9 10 8086 32 31 RD HOLD single microprocessor AD5 AD4 11 12 30 29 HLDA WR AD3 13 28 M/IO  Cheaper since all control signals for AD2 14 27 DT/R memory and I/O are generated by the AD1 AD0 15 16 26 25 DEN ALE microprocessor. NMI INTR 17 18 24 23 INTA TEST Maximum mode CLK GND 19 20 22 21 READY RESET  Pull MN/MX logic 0  Larger systems with more than one processor (designed to be used when a Lost Signals in coprocessor (8087) exists in the system) Max Mode
  8. 8. Minimum-mode and Maximum-mode Signals GND 1 40 VCC GND 1 40 VCC AD14 2 39 AD15 AD14 2 39 AD15 AD13 3 38 A16/S3 AD13 3 38 A16/S3 AD12 4 37 A17/S4 AD12 4 37 A17/S4 AD11 5 36 A18/S5 AD11 5 36 A18/S5 AD10 6 35 A19/S6 AD10 6 35 A19/S6 AD9 7 34 BHE/S7 GND AD9 7 34 BHE/S7 AD8 8 33 MN/MX Vcc AD8 8 8086 33 MN/MX AD7 AD6 9 10 8086 32 31 RD HOLD AD7 AD6 9 10 32 31 RD RQ/GT0 AD5 11 30 RQ/GT1 AD5 11 30 HLDA AD4 12 29 LOCK AD4 12 29 WR AD3 13 28 S2 AD3 13 28 M/IO AD2 14 27 S1 AD2 14 27 DT/R AD1 15 26 S0 AD1 15 26 DEN AD0 16 25 QS0 AD0 16 25 ALE NMI 17 24 QS1 NMI 17 24 INTA INTR 18 23 TEST INTR 18 23 TEST CLK 19 22 READY CLK 19 22 READY GND 20 21 RESET GND 20 21 RESET Min Mode Max Mode
  9. 9. 8086 System Minimum mode PC LK+5V C lo c k C LK M /IO R EA D Y C o n tr o l g e n e r a to r IN T A R ES R ES ET Bus R D AE N 2 W R AE N 1 F /C M N /M X +5V W a it - S t a t e ALE STB A0 - A19 G e n e ra to r O E A d d re s s B u s 8282 8086 C PU A D 0 -A D 1 5 L a tc h A 1 6 -A 1 9 BH E BH E D 0 - D 15 8286 16 D T /R T D EN O E
  10. 10. 8086 System Maximum Mode+5V M N /M X G nd CLK M RDC CLK S0 S0 C lo c k READY M W TC RES S1 S1 B u s C o n tr o lle r g e n e ra to r AM W C S2 S2 RESET 8288 IO R C DEN IO W C D T /R A IO W C W a it - S t a t e ALE IN T A G e n e ra to r 8086 C PU STB A0 - A19 O E A d d re s s B u s 8282 A D 0 -A D 1 5 L a tc h BHE A 1 6 -A 1 9 T O E D ATA 8286 T ra n s c e iv e r
  11. 11. Description of the Pins GND 1 40 VCCGND 1 40 VCC AD14 2 39 AD15AD14 2 39 AD15 AD13 3 38 A16/S3AD13 3 38 A16/S3 AD12 4 37 A17/S4AD12 4 37 A17/S4 AD11 5 36 A18/S5AD11 5 36 A18/S5 AD10 6 35 A19/S6AD10 6 35 A19/S6 AD9 7 34 BHE/S7 GNDAD9 7 34 BHE/S7AD8 8 33 MN/MX Vcc AD8 8 8086 33 MN/MXAD7AD6 9 10 8086 32 31 RD HOLD AD7 AD6 9 10 32 31 RD RQ/GT0 AD5 11 30 RQ/GT1AD5 11 30 HLDA AD4 12 29 LOCKAD4 12 29 WR AD3 13 28 S2AD3 13 28 M/IO AD2 14 27 S1AD2 14 27 DT/R AD1 15 26 S0AD1 15 26 DEN AD0 16 25 QS0AD0 16 25 ALE NMI 17 24 QS1NMI 17 24 INTA INTR 18 23 TESTINTR 18 23 TEST CLK 19 22 READYCLK 19 22 READY GND 20 21 RESETGND 20 21 RESET Min Mode Max Mode
  12. 12. RESET Operation results CPU component Contents Flags ClearedInstruction Pointer 0000H CS FFFFH DS, SS and ES 0000H Queue Empty
  13. 13. AD0 - AD15: Address Data Bus DataAD0 – AD15 Address
  14. 14. A17/S4, A16/S3 Address/StatusA17/S4 A16/S3 Function 0 0 Extra segment access 0 1 Stack segment access 1 0 Code segment access 1 1 Data segment access
  15. 15. A19/S6, A18/S5 Address/StatusA18/S5: The status of theinterrupt enable flag bit is updatedat the beginning of each cycle. The status of the flagis indicated through this pinA19/S6: When Low, it indicates that 8086 is incontrol of the bus. During a "Hold acknowledge"clock period, the 8086 tri-states the S6 pin and thusallows another bus master to take control of thestatus bus.
  16. 16. S0, S1 and S2 SignalsS2 S1 S0 Characteristics Interrupt0 0 0 acknowledge0 0 1 Read I/O port0 1 0 Write I/O port0 1 1 Halt1 0 0 Code access1 0 1 Read memory1 1 0 Write memory1 1 1 Passive State
  17. 17. QS1 and QS2 SignalsQS1 QS1 Characteristics0 0 No operation0 1 First byte of opcode from queue1 0 Empty the queue1 1 Subsequent byte from queue
  18. 18. Read Write Control SignalsIO/M DT/R SSO CHARACTERISTICS 0 0 0 Code Access 0 0 1 Read Memory 0 1 0 Write Memory 0 1 1 Passive 1 0 0 Interrupt Acknowledge 1 0 1 Read I/O port 1 1 0 Write I/O port 1 1 1 Halt
  19. 19. 8086 Memory AddressingData can be accessed from the memory in fourdifferent ways:• 8 - bit data from Lower (Even) address Bank.• 8 - bit data from Higher (Odd) address Bank.• 16 - bit data starting from Even Address.• 16 - bit data starting from Odd Address.
  20. 20. Treating Even and Odd Addresses H ig h e r Low er A d d re s s A d d re s s Bank Bank (5 1 2 K x 8 ) BHE (5 1 2 K x 8 ) A0 ODD EVENA 1 -A 1 9 D 8 -D 1 5 D 0 -D 7A d d re s s B u s D a ta B u s ( D 0 - D 1 5 )
  21. 21. 8-bit data from Even address Bank O dd B an k E ven B a n k x + 1 x x + 3 x + 2 x + 5 x + 4 B H E = 1 A 0 = 0 D 8 -D 1 5 D 0 -D 7A 1 -A 1 9D 0 -D 1 5 MOV SI,4000H MOV AL,[SI+2]
  22. 22. 8-bit Data from Odd Address Bank O dd B ank Even Bank x + 1 x x + 3 x + 2 BH E =0 A0 = 1A 1 -A 1 9 D 0 -D 7 D 8 -D 1 5D 0 -D 1 5 MOV SI,4000H MOV AL,[SI+3]
  23. 23. 16-bit Data Access starting from Even Address O dd B ank Even Bank x + 1 x x + 3 x + 2 A0 = 0 BHE =0 A 1 -A 1 9 D 8 -D 1 5 D 0 -D 7 D 0 -D 1 5 MOV SI,4000H MOV AX,[SI+2]
  24. 24. 16-bit Data Access starting from Odd Address O dd B ank Even Bank O dd B ank Even Bank 0005 0004 0005 0004 0007 0006 0007 0006 0009 0008 0009 0008A 1 -A 1 9 A 1 -A 1 9 A 1 -A 9 A 1 -A 9 D 0 -D 7 D 0 -D 7 D 8 -D 1 5 D 8 -D 1 5 ( a ) F ir s t A c c e s s f r o m O d d A d d r e s s (b ) N e x t A c c e s s fro m E v e n A d d re s s MOV SI,4000H MOV AX,[SI+5]
  25. 25. Read Timing Diagram T 1 T 2 T 3 T w a it T 4C L KA D 0 -A D 1 5B H EA L ES 2 -S 0M /IOR DR E A D YD T /RD E NW R
  26. 26. Write Machine Cycle
  27. 27. INTR (input) Hardware Interrupt Request Pin• INTR is used to request a hardware interrupt.• It is recognized by the processor only when IF = 1, otherwise it is ignored (STI instruction sets this flag bit).• The request on this line can be disabled (or masked) by making IF = 0 (use instruction CLI)• If INTR becomes high and IF = 1, the 8086 enters an interrupt acknowledge cycle (INTA becomes active) after the current instruction has completed execution.
  28. 28. For Discussion• If I/O peripheral wants to interrupt the processor, the “interrupt controller” will send high pulse to the 8086 INTR pin.• What about if a simple system to be built and hardware interrupts are not needed; What to do with INTR and INTA?
  29. 29. NMI (input) Non-Maskable Interrupt line• The Non Maskable Interrupt input is similar to INTR except that the NMI interrupt does not check to see if the IF flag bit is at logic 1.• This interrupt cannot be masked (or disabled) and no acknowledgment is required.• It should be reserved for “catastrophic” events such as power failure or memory errors.
  30. 30. 8086 External Interrupt ConnectionsNMI - Non-Maskable Interrupt INTR - Interrupt Request Programmable NMI Requesting Interrupt Controller Device (part of chipset) NMI8086 CPU Intel INTR Interrupt Logic 8259A PIC Divide Single int into Error Step Software Traps
  31. 31. TEST (input)• The TEST pin is an input that is tested by the WAIT instruction.• If TEST is at logic 0, the WAIT instruction functions as a NOP.• If TEST is at logic 1, then the WAIT instruction causes the 8086 to idle, until TEST input becomes a logic 0.• This pin is normally driven by the 8087 co- processor (numeric coprocessor) .• This prevents the CPU from accessing a memory result before the NDP has finished its calculation
  32. 32. Ready (input)• This input is used to insert wait states into processor Bus Cycle.• If the READY pin is placed at a logic 0 level, the microprocessor enters into wait states and remains idle.• If the READY pin is placed at a logic 1 level, it has no effect on the operation of the processor.• It is sampled at the end of the T2 clock pulse• Usually driven by a slow memory device
  33. 33. 8284 Connected to 8086 Mp X1 Ready X2 AEN1 CLK AEN2 F/C 8284 ResetRDY1RDY2 RES R+5V or ci M6808 RESET KEY C
  34. 34. HOLD (input)• The HOLD input is used by DMA controller to request a Direct Memory Access (DMA) operation.• If the HOLD signal is at logic 1, the microprocessor places its address, data and control bus at the high impedance state.• If the HOLD pin is at logic 0, the microprocessor works normally.
  35. 35. HLDA (output) Hold Acknowledge Output• Hold acknowledge is made high to indicate to the DMA controller that the processor has entered hold state and it can take control over the system bus for DMA operation.
  36. 36. DMA Operation

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