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RISC-V growth and successes in technology and industry - embedded world 2021

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RISC-V growth and successes in technology and industry - embedded world 2021

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RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is projected that by 2025 there will be over 62 billion RISC-V CPU cores and the total market for RISC-V IP and software is expected to grow to over $1b by 2025.  

In 2020 alone, we saw successes with newly defined RISC-V accelerator architectures, affordable RISC-V open source small-board computers, development boards for personal computers, and an incredibly fast 64-bit RISC-V Core as the community also ratified key specifications and made advances in security. 

As we see the growth of RISC-V into industries such as AI, machine learning, blockchain, 5G, medical, and industrial, we will see the ratifications of new extensions that enable this growth.

Join Kim McMahon, Director of Marketing and Stephano Cetola, Technical Program Manager as we take a look at where RISC-V is going in 2021.

RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is projected that by 2025 there will be over 62 billion RISC-V CPU cores and the total market for RISC-V IP and software is expected to grow to over $1b by 2025.  

In 2020 alone, we saw successes with newly defined RISC-V accelerator architectures, affordable RISC-V open source small-board computers, development boards for personal computers, and an incredibly fast 64-bit RISC-V Core as the community also ratified key specifications and made advances in security. 

As we see the growth of RISC-V into industries such as AI, machine learning, blockchain, 5G, medical, and industrial, we will see the ratifications of new extensions that enable this growth.

Join Kim McMahon, Director of Marketing and Stephano Cetola, Technical Program Manager as we take a look at where RISC-V is going in 2021.

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RISC-V growth and successes in technology and industry - embedded world 2021

  1. 1. RISC-V Growth and Successes in Technology and Industry embedded world 2021 Kim McMahon Director of Marketing RISC-V International @kamcmahon Stephano Cetola Technical Program Manager RISC-V International @stephano
  2. 2. Welcome to the RISC-V presentation! Meet: Kim McMahon Director of Marketing Kim has a deep background in open source and technology. She has spent her career with companies such as SGI, Cray, VMware, and the {code} Team at Dell, where she honed her love for HPC, open source, and cloud native. A long-time Colorado girl, she lives in Winter Park, Colorado and enjoys hiking, skiing, and outdoor activities with her two labradors Coal and Connor. Stephano Cetola Program Manager Stephano is a technical program manager for RISC-V International. He has worked on and managed numerous open source initiatives in software and hardware. Before joining the RISC-V team, Stephano was employed at Intel contributing to the Yocto Project building embedded Linux distros and working on TianoCore, an open source implementation of UEFI. He is involved in research at Portland State University focusing on Trusted Execution Environments and hardware security testing. @kamcmahon @stephano
  3. 3. Who is RISC-V? RISC-V is the free and open ISA ... Driven through Open collaboration ... Enabling freedom of design across all domains and industries ... Cementing the strategic foundation of semiconductors Welcome to the Open era of computing! @risc_v @kamcmahon @stephano
  4. 4. 2020 was amazing! Technical: RISC-V Processor trace specification ratified In the news... ● BBC Learning and Tynker released the BBC Doctor Who HiFive Inventor to engage the next generation of coders. ● Imagination Technologies partnered with RIOS Laboratory to enable RIOS Lab to build a complete development platform and open-source ecosystem for RISC-V single-board computers. ● The European Processor Initiative finalized the first version of its RISC-V accelerator architecture, named EPAC. And from (some) of our members ● Alibaba unveiled its RV64GCV core that will be used for its Xuantie 910 processor aimed at cloud and edge servers. ● Andes released new superscalar multicore processors and processors with Level-2 (L2) cache controller. ● GreenWaves Technologies announced its ultra-low power GAP9 hearables platform that enables scene-aware active noise cancellation and neural network-based noise reduction. ● Imperas Software debuted a reference model with UVM encapsulation for RISC-V verification. ● OpenHW Group implemented Imperas RISC-V reference models for coverage driven verification of open source CORE-V processor IP cores. @risc_v @kamcmahon @stephano
  5. 5. 2021 will be even better! Compatibility Framework & Architectural Tests ● Each new ISA extension requires tests ● RISC-V ISA Coverage with RISC-V ISAC ● RISC-V Compliance Test Generator with RISC-V CTG Embedded Groups ● Code Size, Fast Int, P Ext ● Embedded ABI (EABI) ● Software Overlay ● Standalone Debug ● Trusted Execution (TEE) Ratifications ● Vector Extensions ● Cryptography ● Virtual Memory ● Bit Manipulation @risc_v @kamcmahon @stephano
  6. 6. Embedded Task Groups Software Overlay ● Lead by Western Digital & Embecosm ● Focused on loading code in Real-Time ● CoversFW manager engine and toolchain Fast Interrupt Scheme ● Low-latency, Vectored, Priority-based, preemptive ● Hardware specifications and software ABIs/APIs ● Standardize compiler conventions for annotating handler functions @risc_v @kamcmahon @stephano
  7. 7. Embedded Task Groups Code Size ● Holistic solution to reducing code size ● Priority given to small embedded cores ● Improved toolchain technology Packed SIMD (P Extension) ● SIMD instructions on 8b, 16b, & 32b integer data types ● Non-SIMD DSP instructions on 16b, 32b & 64b ● Support saturation and rounding ● QEMU, Spike (sim), & toolchain work ongoing @risc_v @kamcmahon @stephano
  8. 8. Enhanced Security Features Extended Physical Memory Protection (PMP) ● Supervisor Mode Access/Execution Prevention ● Machine Security Configuration (mseccfg) ​machine mode CSR Supervisor-mode PMP ● Provides per thread s-mode control registers IO PMP ● Protects physical memory from all memory masters ● Supports scalable number of entries and error reporting @risc_v @kamcmahon @stephano
  9. 9. What’s next Participate! ● Join a working group: https://lists.riscv.org ● Become a member: https://riscv.org/membership/ Even Non-members Can Contribute ● https://github.com/riscv ● https://groups.google.com/a/groups.riscv.org Want to continue the conversation with RISC-V! Jump over to the RISC-V Slack, Embedded World channel. risc-v-international.slack.com @risc_v @kamcmahon @stephano
  10. 10. Thank you Visit our partners!
  11. 11. RISC-V Forums! Short-form, single-topic events Submit CFP: Submissions close March 5 Register! Security Embedded Technology Developer Tools and Tool Chains Embedded Industry

Editor's Notes

  • nadiska.beer@nuernbergmesse.de

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