1.
Fueling the Datasphere
How RISC-V Enables the Storage Ecosystem
RISC-V SUMMIT 2020
Richard Bohn
Engineering Director

2.
01 Our RISC-V Story
02 Microprocessor Details
03 RISC-V at the Edge

3.
Our RISC-V Story

4.
Seagate is the Data Storage Industry Leader
$10B+
Annual Revenue
400+ EB
Shipped Annually Storage Innovation
40+ Years
World’s Data Stored
40%

5.
Expertise Across all Technology Fields
5+ Global
Storage System OEMs Cloud Providers
5+ Leading
Technology Companies
5+ Global
We provide storage infrastructure for most of the world's data.

6.
Background
Global Data Explosion
• Market transformations driving new storage needs
• Mainframe → client-server → mobile-cloud → edge
• Data creation expected to grow to 175ZB by 2025
RISC-V in the Storage Ecosystem
• New technologies are driving new processing requirements
• RISC-V meets those needs in a way not met by the marketplace
• The edge requires new security and computation innovation
• RISC-V driving new wave of innovation in domain-specific solutions
Enabling Technologies
• Heat-assisted magnetic recording (HAMR) driving capacity gains
• MACH.2 multi-actuator technology enables high-performance
access to mass quantities of data generated on the edge

7.
Seagate’s RISC-V Story
2019-
Today
Origins of RISC-V Work
• For years, Seagate shipped a simple internally-designed CPU with a custom ISA
• Firmware developed using a fancy assembler, but no real compiler support
• In 2015, Seagate decided to develop compiler support for this CPU as a side project
• Discovered the RISC-V project and decided to instead design a new CPU
• New CPU soon grew to be an aggressive out-of-order core
Production-Capable Development
• Tuned processor design point to target internal workloads
where performance needs not being met with existing solutions
• Expanded efforts to support production-quality feature set and verification
• Actively engaged RISC-V community and standards development
Next-Generation Capabilities
• Next-generation development targeting new workloads
• New area-optimized core targeting auxiliary and security applications
• Coherent fabric development for multi-core deployments
2017-
2018
2015-
2016

8.
Solving Domain-Specific Pain Point of Real-Time Processing
Microarchitecture optimization,
parallelism, and latency reduction
Seagate RISC-V Core
Legacy Core
Disturbance detection filter
(computational cycles)
3× Reduction
RISC-V-Enabled Solution
Functional Example:
Motion Control Use Case
Hard drive capacity is projected
to exceed 50TB by 2026
At 50TB, track density will exceed
1 million tracks per inch (TPI)
(2.4 nm positioning accuracy)
The Problem
Multi-stage actuators for coarse
movement and fine positioning
Real-Time Processing
• Disturbance detection algorithms
• Adaptive control features
• Feed-forward compensation
• High sample-rate computation
Constraints
• Power, space, and cost
The Required Innovation

9.
Microprocessor Details

10.
Seagate’s First RISC-V High-Performance Core
• Started development in 2015
• Highly configurable microarchitecture
and feature set
• Powering a fully functional
hard drive demonstration
• Combines features needed by real-time
control applications with performance
capabilities required for future workloads
• Initial deployment targeting high-performance
servo-actuator control workload
Overview

11.
High-Performance Core
Technical Details (Current Silicon)
• RV32IMFCN
• Machine and user modes
• Speculative out-of-order pipeline
• 4-wide fetch and dispatch
• 8-wide issue (peak)
• High-performance instruction fetch: branch
prediction, return address stack, loop buffer
• Dual-ported load-store unit
• Large L1 tightly-integrated memories
• Multi-way L1 caches
• Decoupled high-performance FPU
• PLIC (Platform-Level Interrupt Controller​)
• Native ECC support
• RISC-V Debug and Trace Support

12.
High-Performance Core Pipeline
Address
generation
Alignment,
rotation,
error
correction Fetch buffer
IW, FPW,
LSQ, ROB
entries
dispatched
IW, FPW
entries
valid
LSQ, RU
entries
valid LSU result
formatting
and store
forwarding
application,
write-back of
loads
LSU SRAM
access,
store
forward
search
Retirement,
exception
handling
Execute and write-
back of most integer
ops, LSU AGEN
Issue
search
SRAM
access
Decode,
register
rename

13.
High-Performance Core Pipeline

14.
Seagate High-Performance Core
1.00 1.00 1.00
0.77
0.93 0.86
2.04
3.12
3.26
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
Internal Workload #1 Internal Workload #2 Internal Workload #3
Processor A Processor B Seagate High-Performance Core

15.
Area-Optimized Cores
Overview
• Began development in 2019
• Highly configurable microarchitecture
and feature set
• Enables auxiliary workloads
and security applications
• Targets small-footprint implementation
of features over performance

16.
Area-Optimized Cores
Technical Details
• RV32/64IMCBN
• Machine, supervisor, and user modes
• SV39/SV32
• 5-stage, single-issue, in-order pipeline
• CLIC (Core-Local Interrupt Controller)
• Enhanced PMP
• Focus on optional security features
• Native ECC support
• RISC-V debug and trace

17.
RISC-V at the Edge

18.
RISC-V at the Edge
Challenges of
Data Movement
• Edge devices generate
massive amounts of data
• Connectivity to the
cloud is not sufficient
to transport all data
• How to quickly make
decisions based on this
massive amount of edge
data? Need computation
on edge devices.
• How to keep data at the
edge secure and trustworthy?
RISC-V Enables
Innovation at the Edge
• Workloads are
numerous and varied
• Constraints on power
and latency limit
current applications
• Domains-specific
architectures enable
use cases not previously
possible with general
purpose solutions
• RISC-V opens up domain-
specific computation to all
RISC-V Strengthens
Security at the Edge
• Open, formally-proven
security models
• Best-in-class protections
built in collaboration with
top security experts
across many companies

19.
RISC-V at the Edge
More RISC-V Summit 2020 Talks
• “RISC-V: Accelerating Innovation
in Data Storage” – Dr. John Morris
• “Data on the Move: A RISC-V
Opportunity” – Bruno Masson
• “Comprehensive Pre-Si Verification of
RISC-V Cores in a Storage Controller”
– Bill McSpadden
• “Data Trustworthiness at the Edge”
– Manuel Offenberg
1.00
3.04
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
Seagate HPC Seagate HPC + Custom Tensor Ops
AI Inference Performance

20.
The Power of the RISC-V Ecosystem
RISC-V Enables CPU Development for the Masses
• CPU development is challenging, but RISC-V’s
robust ecosystem makes it much easier
• Strong commercial support is available
for all phases of the design process
• Direct collaborations through specification
development enrich everyone. Get involved!
RISC-V International Strategic Member Representation
• Seagate is honored to serve on the RISC-V International Board
of Directors as a representative for the strategic class of members
• Feel free to reach out to Richard Bohn at richard.bohn@seagate.com
with your thoughts on the future of RISC-V International

21.
Thank you
Richard Bohn
richard.bohn@seagate.com
RISC-V SUMMIT 2020