These presentations are prepared from Verilog HDL book from Samir Palnitkar. The presentations were prepared for 5th Semester ECE Verilog HDL (15EC53)

1. VERILOG-HDL
15EC53
Prabhavathi P
Associate Professor
Department of ECE.
B N M Institute of Technology,
12th Main, 27th Cross,
B S K II stage,
Bengaluru - 560070

2. OUTLINE
Gate-level modeling
Data-flow modeling
Behavioral modeling
Basics of the Verilog Language
Text book : Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir

3. VERIL
OG
HDL
(CONT
INUE)
• Invented by Philip Moorby in 1983/ 1984 at
Gateway Design Automation ( Prabhu Goel,
President )
• Enables specification of a digital system at a range
of levels abstraction: switches, gates, RTL,
and higher
• Initially developed in conjunction with the
Verilog simulator
VERILOGHDL

4. VERILOGHDL
• Verilog- based synthesis tool introduced by
Synopsys in 1987
• Gateway Design Automation bought by Cadence
in 1989
• Verilog placed in public domain to compete with
VHDL
-Open Verilog International (OVI) IEEE 1364 -
1995
-revised version IEEE 1364 -2001
-revised version IEEE 1364 -2001

6. 2005
Verilog HDL 6
HISTORYOFVERILOG®HDL(CONT’D)
Three factors to success of Verilog
Programming Language Interface (PLI)
Extend and customize simulation environment
Close attention to the needs of ASIC foundries
“Gateway Design Automation” partnership with
Motorola, National, and UTMC in 1987-89
Verilog-based synthesis technology
“Gateway Design Automation” licensed Verilog to
Synopsys
Synopsys introduced synthesis from Verilog in 1987

7. 2005
Verilog HDL 7
HISTORYOFVERILOG®HDL(CONT’D)
VHDL
• VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language
• Developed under contract from DARPA
• IEEE standard
• Public domain
• Other EDA vendors adapted VHDL
• “Gateway” put Verilog in public domain

8. 2005
Verilog HDL 8
HISTORYOFVERILOG®HDL(CONT’D)
Today
• Market divided between Verilog & VHDL
 VHDL mostly in Europe
 Verilog dominant in US
• VHDL
 More general language
 Not all constructs are synthesizable
• Verilog:
 Not as general as VHDL
 Most constructs are synthesizable

9. 2005
Verilog HDL 9
TYPICALDESIGNFLOW(CONT’D)
NOTE:
CAD tools help, but the designer still has the main role
GIGO (Garbage-In Garbage-Out) concept
To obtain an optimized design, the designer needs to
know about the synthesis technology
Compare to software programming and compilation

10. 2005
Verilog HDL 10
IMPORTANCEOFHDLS
• Retargeting to a new fabrication technology
• Functional verification earlier in the design
cycle
• Textual concise representation of the design
• Similar to computer programs
• Easier to understand

11. 2005
Verilog HDL 11
POPULARITYOFVERILOGHDL
Verilog HDL
• General-purpose
• Easy to learn, easy to use
• Similar in syntax to C
• Allows different levels of abstraction and mixing
them
• Supported by most popular logic synthesis tools
• Post-logic-synthesis simulation libraries by all
fabrication vendors
• PLI to customize Verilog simulators to designers’
needs

12. WHA
TIS
VERIL
OG
HDL?
Mixed level modeling
Behavioral
Algorithmic ( like high level language)
Register transfer (Synthesizable)
Structural
Gate (AND, OR ……)
Switch (PMOS, NOMS, JFET ……)
• Single language for design and simulation
• Built-in primitives and logic functions
• User-defined primitives
• Built-in data types
• High-level programming constructs

13. BASICCONVENTIONS
• Verilog is case sensitive
– Keywords are in lowercase
• Extra white space is ignored
– But whitespace does separate tokens
• Comments
– One liners are //
– Multiple lines /* */
– Comments may not be nested

14. BASICSOFTHEVERILOGLANGUAGE
Basics of the Verilog Language
• Overview of Verilog Module
• Identifier & Keywords
• Logic Values
• Data Types
• Numbers & Negative Numbers
• Gate-level modeling
• Data-flow modeling
• Behavioral modeling
• Task and function

15. OVER
VIEW
OF
VERIL
OG
MOD
ULE
Test bench

16. BASIC
UNIT-
-
MOD
ULE
module module_name (port_name);
port declaration
data type declaration
module functionality or structure
endmodule
Typicalmodulestructure

17. D-FLIPFLOP
module D_FF(q,d,clk,reset);
output q; //port declaration
input d,clk,reset; // data type declaration
reg q;
always @ (posedge reset or negedge clk)
if (reset)
q=1'b0;
else
q=d;
endmodule

18. INSTANCE
• A module provides a template which you can
create actual objects.
• When a module is invoked, Verilog creates a
unique object from the template
• The process of creating a object from module
template is called instantiation
• The object is called instance

19. INSTANCES
module adder (in1,in2,cin,sum,cout);
.......
endmodule
module adder8(....) ;
adder add1(a,b,1’b0,s1,c1) ,
add2(.in1(a2),.in2(b2),.cin(c1),.sum(s2)
,.cout(c2)) ;
.....
endmodule
Mapping port positions
Mapping names

20. 2005
Verilog HDL 20
VERILOGBASICBUILDINGBLOCK
Module
module not_gate(in, out); // module name+ports
// comments: declaring port type
input in;
output out;
// Defining circuit functionality
assign out = ~in;
endmodule

21. 2005
Verilog HDL 21
USELESSVERILOGEXAMPLE
module useless;
initial
$display(“Hello World!”);
endmodule
Note the message-display statement
Compare to printf() in C

22. T-FLIPFLOP
module T_FF(q,clk,reset);
output q;
input clk,reset;
wire d;
D_FF dff0(q,d,clk,reset); // create an instance
not n1(d,q);
endmodule

23. IDENTIFIER&KEYWORDS
Identifier
User-provided names for Verilog objects in the descriptions
Legal characters are “a-z”, “A-Z”, “0-9”, “_”, and “$”
First character has to be a letter or an “_”
Example: Count, _R2D2, FIVE$
Keywords
Predefined identifiers to define the language constructs
All keywords are defined in lower case
Cannot be used as identifiers
Example: initial, assign, module, always….

24. 2005
Verilog HDL 24
DESIGNMETHODOLOGIES

25. 2005
Verilog HDL 25
4-BITRIPPLECARRYCOUNTER

26. 2005
Verilog HDL 26
T-FLIPFLOPANDTHEHIERARCHY

27. 2005
Verilog HDL 27
MODULES
module <module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule
Example:
module T_ff(q, clock, reset);
...
<functionality of T_flipflop>
...
endmodule

28. 2005
Verilog HDL 28
MODULES(CONT’D)
Verilog supported levels of abstraction
Behavioral (algorithmic) level
Describe the algorithm used
Very similar to C programming
Dataflow level
Describe how data flows between registers and is processed
Gate level
Interconnect logic gates
Switch level
Interconnect transistors (MOS transistors)
Register-Transfer Level (RTL)
Generally known as a combination of behavioral+dataflow that is
synthesizable by EDA tools

29. 2005
Verilog HDL 29
INSTANCE
S
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module TFF are created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);
endmodule

30. 2005
Verilog HDL 30
INSTANCES(CONT’D)
module TFF(q, clk, reset);
output q;
input clk, reset;
wire d;
DFF dff0(q, d, clk, reset);
not n1(d, q); // not is a Verilog provided primitive.
endmodule
// module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule

31. 2005
Verilog HDL 31
INSTANCES(CONT’D)
Illegal instantiation example:
Nested module definition not allowed
Note the difference between module definition and module
instantiation
// Define the top level module called ripple carry
// counter. It is illegal to define the module T_FF inside
// this module.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
:
<module T_FF internals>
:
endmodule // END OF ILLEGAL MODULE NESTING
endmodule

32. 2005
Verilog HDL 32
SIMULATION-TESTBENCHSTYLES

33. 2005
Verilog HDL 33
EXAMPLE
Design block was shown before
ripple_carry_counter, T_FF, and D_FF modules
Stimulus block

34. 2005
Verilog HDL 34
EXAMPLE(CONT’D)
module stimulus;
reg clk; reg reset; wire[3:0] q;
// instantiate the design block
ripple_carry_counter r1(q, clk, reset);
// Control the clk signal that drives the design block.
initial clk = 1'b0;
always #5 clk = ~clk;
// Control the reset signal that drives the design block
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $stop;
end
initial // Monitor the outputs
$monitor($time, " Output q = %d", q);
endmodule

35. EXAMPLE
4-bit adder
module Ripple_Add(s,c3,ci,a,b)
input [3:0] a,b ; // port declarations
input ci ;
output [3:0] s : // vector
output c3 ;
wire [2:0] co ;
FA fa0(co[0], s[0], a[0], b[0], ci) ;
FA fa1(co[1], s[1], a[1], b[1], co[0]) ;
FA fa2(co[2], s[2], a[2], b[2], co[1]) ;
FA fa3(c3, s[3], a[3], b[3], co[2]) ;
endmodule
fa0fa1fa2fa3
c3 ci

36. SAMPLEDESIGN
Module FA( sum, cout, a, b , ci );
// port declaration
output sum, cout;
input a, b, ci;
reg sum, cout;
// behavior description
always @( a or b or ci )
begin
sum = a ^ b ^ ci;
cout = ( a&b ) | ( b&ci ) |
( ci&a);
end
endmodule
1-bit full adder
a
b
ci
sum
cout

37. USINGTHEPITCHBOOKTEMPLATE
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My Logo

38. SAMPLE SLIDES

39. ANNUALREPORT
Fiscal Year 2005 Annual Report
Quarter Ended 1st Qtr. 2nd Qtr. 3rd Qtr. 4th Qtr. Total
Fiscal year 2003
Revenue $7,746 $8,541 $7,835 $8,065 $32,187
Gross profit 6,402 6,404 6,561 6,761 26,128
Net income 2,041 1,865 2,142 1,483 7,531
Basic earnings per share 0.19 0.17 0.2 0.14 0.7
Diluted earnings per share 0.19 0.17 0.2 0.14 0.69
Fiscal year 2004
Revenue $8,215 $10,153 $9,175 $9,292 $36,835
Gross profit 6,735 7,809 7,764 7,811 30,119
Net income 2,614 1,549 1,315 2,690 8,168
Basic earnings per share 0.24 0.14 0.12 0.25 0.76
Diluted earnings per share 0.24 0.14 0.12 0.25 0.75
Fiscal year 2005
Revenue $9,189 $10,818 $9,620 $10,161 $39,788
Gross profit 7,720 8,896 8,221 8,751 33,588
Net income 2,528 3,463 2,563 3,700 12,254
Basic earnings per share 0.23 0.32 0.24 0.34 1.13
Diluted earnings per share 0.23 0.32 0.23 0.34 1.12
(1) Includes charges totaling $750 million (pre-tax) related to the Fabrikam settlement and
$1.15 billion in impairments of investments.
(2) Includes stock-based compensation charges totaling $2.2 billion for the employee stock
option transfer program.
(3) Includes charges totaling $756 million (pre-tax) related to Contoso subsidiaries and other
matters.
Market Risk
Fiscal Year 2004
22%
28%25%
25% 1st Qtr
2nd Qtr
3rd Qtr
4th Qtr
0
5000
10000
1st Qtr 2nd Qtr 3rd Qtr 4th Qtr
Gross Profit Net Revenue
0
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150
200
Interest rates Currency rates Equity prices Commodity prices
2004 2005 Average

40. MARKETSUMMARYANALYSIS
Market Distribution1st Year Sales Figures
Our perennial 3rd Quarter boost was larger than expected
contributing to an exceptionally strong year. Distribution of sales
across the geographic markets looks fairly steady.
Our new product line, released this year, is early in its adoption
phase. We expect to see substantial revenue contribution from
these products over the next two years.
Financial Summary
0
20
40
60
80
100
1st Qtr 2nd Qtr 3rd Qtr 4th Qtr
East West North
0
20
40
60
80
100
120
140
160
180
1st Qtr 2nd Qtr 3rd Qtr 4th Qtr
East West North

41. BUSINESSSUMMARY
Market Share by Division
Product Division 2002 2003 2004 2005
Electronics 10.3 % 12.1% 13.2% 17.0%
Consumer Goods 1.3% 2.3% 2.2% 2.7%
Services 12.0% 11.0% 8.9% 9.2%
Widget Sales 78.0% 82.3% 82.5% 84.0%
Installations 5.3% 7.9% 12.2% 15.1%
(1) Percentages based on domestic comparison to competitors in directly related
industries.
(2) Percentages based on standing at the end of each fiscal year.
(3) Values provided by a third party agency.
Organizational Structure
Contoso
Product
Development
Design Manufacturing
Quality
Assurance
Human
Resources
Headquarters Subsidiaries
Finance
Business Process Model
Summary
This has been a pivotal year for the company in growth, but also
development of our infrastructure and business processes. We’ll
continue to focus on our internal systems over the next year.
Specific growth areas include Electronics where Contoso has seen
as 6.7% increase in market share over the last three years. An area
to monitor closely is the Services division where market share has
dropped slightly.
Operating
Supporting
Optimizing
Changing