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THRIS PROJECT: CSELT HDT COOPERATION

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THRIS PROJECT: CSELT HDT COOPERATION (1997)

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THRIS PROJECT: CSELT HDT COOPERATION

  1. 1. Telecom Hardware Robustness Inspection System Key issue: Achieving global hardware robustness in electronic apparatus
  2. 2. Hardware design phase - signal integrity optimization (ringing, crosstalk, ground bounce, power supply distribution analysis), timing problem control - filtering/shielding optimization (EMI simulations) - reliability evaluation (components, architectural conceps, thermal analysis) Hardware/Software Integration phase - fault insertion, noise injection, experimental EMI precompliance tests EMC qualification phase - emission/susceptibility conformity tests Overall Fault Tolerance Verification phase - fault insertion Installation phase - environment interaction evaluation (grounding, shielding, EMI tests) Hardware Robustness: a life-cycle issue
  3. 3. THRIS: CSELT/HDT partnership SI XTALK SSN What-If SPRINT PRESTO Faults/noise injection Conducted Radiated ESD Burst _SI _FI _EMC Close field measurements (EASYSCAN, NFA) Precompliance EMC (measurements near field) Conducted noise injection (RFI) EMC prediction Reliability RAP THRIS Physical tests on actual systems Data preparation require simulation performed with Presto
  4. 4. THRIS basic functionalities • Common database (data extracted at design phase are the same used in EMC prediction and qualification (Fault insertion) • Signal integrity prediction • EMI prediction (radiated/conducted emission,conducted susceptibility) • EMI performance optimization (What-If analysis) • Reliability evaluation (RAPSODIA, METRICA) • Fault injection (pin forcing technique) • Noise injection • Electrical/thermal monitoring • EMI precompliance analysis (near-field, common mode currents, conducted susceptibility)
  5. 5. THRIS_FI: Pin forcing 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TIME[uS] -1.30 V -1.30 V -1.30 V -2.00 V 0.00 V -2.00 V 0.00 V -2.00 V 0.00 V -2.00 V 0.00 V FAULT CONTROL ON OFFOFF ON STM1 INPUT STREAM (155 Mbit/s) FAULTY NODE (FIRST STAGE OUTPUT) FAULTY OUTPUT STREAM 32 155Mbit/s output streams 32 155Mbit/s input streams Fault Stage A Stage B Stage C Description: 3 Boards + backplane 32 155Mbit/s streams 6 16x16 switching matrices THRIS simulation model: 50000 circuit elements 35000 nodes 20000 timepoints 20’ simulation time on typ. ws.
  6. 6. 0.0 2.0 4.0 6.0 8.0 10.0 12.0 TIME[nS] -1.9 V -1.7 V -1.5 V -1.3 V -1.1 V -0.9 V -0.7 V -0.5 V 0.0 2.0 4.0 6.0 8.0 10.0 12.0 TIME[nS] -1.9 V -1.7 V -1.5 V -1.3 V -1.1 V -0.9 V -0.7 V -0.5 V 0.0 2.0 4.0 6.0 8.0 10.0 12.0 TIME[nS] -1.9 V -1.7 V -1.5 V -1.3 V -1.1 V -0.9 V -0.7 V -0.5 V Normal operation 5mA current injection 12mA current injection ecl interconnection N output testpoint THRIS_FI: Noise injection
  7. 7. THRIS new development Mainly in EMC field of application: Simulation: common mode, maximum radiation evaluation, close field maps in EASYSCAN Measure: generalized radio frequency noise injection

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