3 d integrated circuits


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3 d integrated circuits

  1. 1.  3D Integrated circuit is a chip which accommodatestwo or more layers of active electronic components They are integrated both horizontally and verticallyonto a single circuit.
  2. 2. To reduce wastage of space on the substrate.To improve interconnections among different wafers.To reduce the length of interconnections which in turnreduces heat dissipation and also RC delays.Can be used to accommodate both homogenous andheterogeneous chips. Thus there is a great urge to switch over from 2D ICs to 3D ICs
  3. 3. •The substrate is divided into blocks•The similar characterized active components are stackedin the same block.•This results in ease of interconnection.•Each block is called a tier.
  4. 4. LOCAL TIERS•Independent responding blocksSEMI-GLOBAL TIERS•Blocks used for intra communicationGLOBAL TIERS•Inter communicating blocks used for clock and power supply
  5. 5. BEAM RECRYSTALLISATION:This method involves deposition of polysilicon.This is used to fabricate TFTs which in turn are used infabrication of 3D ICs.PROCESSED WAFER BONDING:This method bonds processed wafers together, and it isindependent of temperature.SOLID PHASE CRYSTALLISATION:It offers flexibility for fabricating multiple layers, usedmostly for stacking SRAM and EPROM.
  6. 6. TimingEnergy performanceInterconnection structures
  7. 7. In current technologies, timing is interconnect driven.Reducing interconnect length in designs can dramaticallyreduce RC delays and increase chip performance
  8. 8.  Wire length reduction has an impact on the cycletime and the energy dissipationEnergy dissipation decreases with the number oflayers used in the design
  9. 9. 3D Cell Placement Placement by min-cut partitioning3D Global Routing Inter-wafer viasCircuit layout management MAGIC
  10. 10. Natural to think of a 3Dintegrated circuit as beingpartitioned into devicelayers or planesMin cut partitioningalong the 3rd dimension issame as minimizing vias
  11. 11. •Routing in 3D consists of routing a set of alignedcongruent routing regions on adjacent wafers.•Wires can enter from any of the sides of the routingregion in addition to its top and bottom•3D router must consider routing on each of the layersin addition to the placement of the inter-waver vias
  12. 12. ILLUSTRATION OF ROUTING AREAS y y x x z z Detailed routing of net when routing areas are known LOOSE ROUTING DETAILED ROUTING
  13. 13.  MAGIC is an open source layout editor developed at UC Berkeley It is an extension to MAGIC by providing support for Multi-layerIC design. The difference is that it has a new Command “bond”. Bond places inter-layer vias in the design file. Once Two layers are bonded they are treated as one entity.
  14. 14. The 3D Integrated circuits are a great relief tointerconnected IC technologies. This opens up a new era in chip designing which hasmany aspects still to be explored and exploited.These can be used in many facets of our lives likesmartphones,microprocessor based memory stacks etc.Thus it can be concluded that“3D IC – A GREAT UPLIFTMENT TO IC WORLD”