Compared to load unaware packet distribution mechanisms often used in the run to completion model, an event scheduler improves core utilization and better handles dynamic traffic mixes by scheduling packets to cores according to their load. It simultaneously provides both atomicity and packet ordering. Hardware-based event schedulers can also provide low-latency inter-core communication. The libeventdev library from Data Plane Development Kit (DPDK) helps developers leverage the event scheduler model.
About the presenter: Sundar Vedantham, Intel, is a Senior Technical Manager working in the Data Center Group in Allentown, PA. His research interests include network traffic and congestion management, high-speed networking, and theoretical computer models, areas in which he holds patents and has published papers, book chapter & articles. He received his Ph.D. in Computer Science in 1997 from Louisiana State University. He enjoys writing articles in English and Tamil to help improve public understanding of technical details behind the fields he has worked on and to attract young students to get into STEM fields.