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Cache Consistency – Requirements and its packet processing Performance implications

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Packet Processing &
Cache Coherency -101A Primer
By: M Jay
2
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No license (express or implied, by estoppel or otherwise) to any intellectual property rights is...
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Cache Consistency – Requirements and its packet processing Performance implications

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The audio starts at 9:00 due to a glitch while recording.

The topic can be as well stated as “All Processor Accesses are not created equally” – H/W and S/W Synergy – Methods and Mechanism:
- The developers in the audience, throughout the class, will wear different hats – first as a hard design engineer and look at platform design choices.
- Then they will wear the hat of driver developer and see the requirements and assumptions of driver on the hardware behavior.
- Then they will wear the hat of system architect and venture out to find out choices as how s/w and h/w can be in synergy and communicate – thereby potential optimum implementation can be made.

About the presenter: M Jay (Muthurajan Jayakumar) has worked with the DPDK team since 2009. He joined Intel in 1991 and has been in various roles and divisions: 64-bit CPU front side bus architect, 64 bit HAL developer, among others, before he joined the DPDK team. M Jay holds 21 US patents, both individually and jointly, all issued while working at Intel. M Jay was awarded the Intel Achievement Award in 2016, Intel's highest honor based on innovation and results.

The audio starts at 9:00 due to a glitch while recording.

The topic can be as well stated as “All Processor Accesses are not created equally” – H/W and S/W Synergy – Methods and Mechanism:
- The developers in the audience, throughout the class, will wear different hats – first as a hard design engineer and look at platform design choices.
- Then they will wear the hat of driver developer and see the requirements and assumptions of driver on the hardware behavior.
- Then they will wear the hat of system architect and venture out to find out choices as how s/w and h/w can be in synergy and communicate – thereby potential optimum implementation can be made.

About the presenter: M Jay (Muthurajan Jayakumar) has worked with the DPDK team since 2009. He joined Intel in 1991 and has been in various roles and divisions: 64-bit CPU front side bus architect, 64 bit HAL developer, among others, before he joined the DPDK team. M Jay holds 21 US patents, both individually and jointly, all issued while working at Intel. M Jay was awarded the Intel Achievement Award in 2016, Intel's highest honor based on innovation and results.

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