S. Deleonibus Essderc 2009

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S. Deleonibus Essderc 2009

  1. 1. 2008 Electronic Devices Architectures for the NANO-CMOS Era. From Ultimate CMOS Scaling to Beyond CMOS devices S.Deleonibus, CEA-LETI, MINATEC, CEA-Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 France. Tel : 33 (0)4 38 78 59 73 Fax: 33 (0)4 38 78 51 83 email: sdeleonibus@cea.fr © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 1
  2. 2. 2008 Outline •Introduction : Facts on context and ITRS •Scaling of Si MOSFET Materials boosters: HiK, back to metal gate!, MOSFET scaling: channel engineering ; FD SOI & boosted SOI Multigate, Nanowires Source and drains technology •Alternative Architectures and Materials Boosters for continued Nanoelectronics scaling Opportunities for other Materials on Silicon? Alternatives for Non Volatile Memories boosters facing a brick wall 3D styles integration on Silicon: monolithic, Is there a «Beyond CMOS»? •Conclusions © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 2
  3. 3. 2008 Scaling: a success story…thanks to innovation Moore’s law: 2Xdevices/year Convergence Portable Digital 1,00E+10 Internet Camera 4G 2G 1G 1,00E+09 1 billion Home 512M ULK(11 lev met) PC 256M rs Office 128M ss o polymers ) 1,00E+08 PC A M 64M o ce Itanium r +ALD (10 lev met) DR Number of transistors per chip op i es( 16M i cr Pentium IV 10 millions or m HiK +metal gate 1,00E+07 e m Pentium III m 4M Main ic Cu+H(M)SQ (9 lev met) am 1M 1,00E+06 Frame d yn Pentium II VCR 256k Pentium Cu (7 lev met) Defense i486 FSG(6 lev met) 64k 100µm 1,00E+05 i386 damascene(5 lev met) Critical Dimension 16k 80286 vias « plugs »,CMP(4 lev met) 1,00E+04 8086 10µm 4k STI, salicide C.T.V. 1k 8080 contacts « plugs »(3 lev met) 1,00E+03 4004 1µm 1,00E+02 0,10µm polycide 1,00E+01 10 nm poly gate 1,00E+00 1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018 Date Electronic Device Architectures for the Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisationTous droits réservés. © CEA 2006. écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA Editor: S.Deleonibus, Pan Stanford Publishing, Oct 2008 S.Deleonibus, ESSDERC Short Course, September 2009 3
  4. 4. 2008 Semiconductor Market applications successive waves Source : Semico Research Corp. May 2004 IPI Report © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 4
  5. 5. 2008 Nomadic consumer and professional products: largest market share continuously increasing Three major product families (ITRS aware of CMOS scaling limits) • High Performance (HP) t=CV/I – Connection to power network • Low Operating Power (LOP) – Intermittent Nomadic Function • Low Stand-by Power (LSTP) Pstat= VddxIoff – Permanent Nomadic Function Pdyn=CVdd2 f Ptot=Pstat+ Pdyn © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 5
  6. 6. 2008 Roadmap of the roadmap: acceleration and… smooth slow down ITRS forecast evolution 2025 125 14nm(5nm) 11nm(4.5nm) 16nm(6nm) 2020 120 18nm(7nm) 22nm(9nm) Production start 2015 115 35nm(25nm) 32nm(13nm) 50nm(35nm) 70nm(50nm) 45nm(18nm) 110 2010 100nm(70nm) 65nm(25nm) 105 2005 130nm(100nm) 100nm(45nm) 180nm(140nm) 2000 100 130nm(65nm) 1995 250nm 95 1994 94 1997 1998 99 97 98 1999 2001 2003 105 107 101 103 2005 2007 Date roadmap Electronic Device Architectures for the Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices Editor: S.Deleonibus, Pan Stanford Publishing, Oct 2008 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 6
  7. 7. 2008 Lg=3.8nm MOSFET S-D Suk et al, VLSI Tech Symposium, Kyoto 2009,p142(Samsung) © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 7
  8. 8. 2008 Ecological Footprint of ICTs reported by Intergovernmental Panel Climate Change(IPCC) • Currently, 3 % of the world-wide energy is consumed by the ICT infrastructure – which causes about 2 % of the world-wide CO2 emissions – comparable to the world-wide CO2 emissions by airplanes or ¼ of the world-wide CO2 emissions by cars • ICT: 10% of electrical energy in industrialized nations – 900 Bill.. kWh / year = Central and South Americas • The transmitted data volume increases approximately by a factor of 10 every 5 years Source: TU Dresden © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 8
  9. 9. 2008 Outline •Introduction : Facts on context and ITRS •Scaling of Si MOSFET Materials boosters: HiK, back to metal gate!, MOSFET scaling: channel engineering ; FD SOI & boosted SOI Multigate, Nanowires Source and drains technology •Alternative Architectures and Materials Boosters for continued Nanoelectronics scaling Opportunities for other Materials on Silicon? Alternatives for Non Volatile Memories boosters facing a brick wall 3D styles integration on Silicon: monolithic, Is there a «Beyond CMOS»? •Conclusions © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 9
  10. 10. 2008 Scaling supply voltage challenges on MOSFET P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f Issues to address(trade of Performance & Power): room temperature operation threshold voltage control parasitic effects The most severe constraints are due to : doping concentration fluctuations, small volume,asymetry FDSOI : low channel doping (reduced variability) short channel effects low ∆VT vs. VT - low Vsupply - Tox thickness,doping concentration, Xj leakage current in subthreshold regime even with S=60mV/dec(FDSOI) and VT = 0,20V (Vsupply=0,5V) we will get Ioff = 1nA/ m tunnel currents SiO2 tunneling dielectric , F-N high doping level, direct tunneling between S/D © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 10
  11. 11. 2008 Statistical dopant fluctuations in a bulk device • random distribution of channel dopants – Poisson’s law: σdoping = √ N/volume • number of dopants in the active area decreases with scaling – statistical fluctuations of threshold voltage: 150 mV VT decay for VT=200mV( Lg=25nm) 4 1 10 σ N/N Nombre d'impuretés 1000 0.1 100 0.01 10 0.01 0.1 1 Lg (µm) S.Deleonibus et al. ESSDERC 1999 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 11
  12. 12. 2008 Classical MOSFET scaling Channel length K Voltage U Gate oxide K Junction depth K Electric field U/K2 Channel doping U/K Parasitic capacitance K(ACox,ACj) Current (vel. sat.) U2/K(U) Delay(vel. sat.) K2/U(K) Power (vel. sat.) U3/K(U2) Speed.Power product KU2 After Baccarani et al. IEDM 1984 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009
  13. 13. 2008 Linear Down scaling trends H.Iwai, Microelectronic Engineering 86 (2009) 1520–1528 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 13
  14. 14. 2008 Information technology based on switching What is the smallest energy needed to qualify an information bit ? (noise, power consumption, « make it green something »,…) Switching devices characteristics : • Heisenberg’s uncertainty principle E ≥ h Emin = 10 −5 aJ τ • Statistical mechanics. Entropy maximization E ≥ kTLnΩ E ≥ 3.10 −3 aJ ( Ω accessible states: 2 in binary system) N .τ mbf 1/ 2    N .τ mbf   kTLn( ) τ • Systems statistical failures E ≥ kTLn  τ   Vmin E ≥ 0.25aJ =  CL       Vmin≈10mV   • Electrostatics Short channel effects: DIBL, Charge sharing,… (CL=0.4fF) • Variability (inherent process characteristics, process perfomances,…) Electrostatics and variability are the 1st order limitation to scaling ε tox x j   1/ 2 W 2  ∂Vt  ∂Vt 2   ∆VT = −4ϕ F 1 + 2  − 1 σ Vt , SCE ∝  σL + ε ox L W  xj   ∂ T σ TSi     ∂L       Si Design: • Device operation mode : 4 th independent electrode, Dynamic threshold,… • Design/technology specific solutions: interconnect, local/global clock (multicores), mixed logic/memory © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 14
  15. 15. 2008 Increasing part of leakage current in power consumption Source: Yasushi Yamagata and Kiyotaka Imai NEC Electronics Corp., Advanced Device Development Div., Solid State Technology, November, 2004 Initially published in Nikkei Microdevices (SST partner) © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 15
  16. 16. 2008 High K dielectric integration:Replacing SiO2 1.E+03 25 EOT, planar bulk bulk J g, simulated for SiON, planar bulk 1.E+02 20 1.E+01 Tox Jg (A/cm2) 15 1.E+00 EOT, UTB FD EOT, UTB FD U0 direct tunneling EOT (A) 1.E-01 10 - E 1.E-02 Jg, limit for SiON, planar bulk EOT, DG EOT, DG 5 1.E-03 High -k needed beyond this High-k beyond this  4π  2mq (U 0 − E )Tox  crossover point point 1.E-04 0 P = exp  − 2005 2007 2009 2011 2013 Calendar Year 2015 2017 2019  h  Tox=1.2nm Active area(10cm2 circuit): 1cm2 Pstat(0.5V)= 5W => 500W/m2(1/2 AM1) Pstat(1V) = 50W => 5kW/m2 Pstat(1.5V) = 750W !! => 75kW/m2!! (Small Nuclear Power station installed power!!) © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 16
  17. 17. HiK gate dielectrics ti =tox εi 2008 εox H. Iwai et al., IEDM Tech Digest 2002, pp. 625-627, Dec 2002, San Francisco(CA). High K Si Gate material (poly,metal) © CEA 2006. Tous droits réservés. SixOxN y Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA or large mobility gap S.Deleonibus, ESSDERC Short Course, September 2009 17
  18. 18. 2008 By courtesy: H.Iwai, TIT © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 18
  19. 19. 2008 High K dielectrics: transistor optimization A.Poncet et al. SISPAD 2001 Short channel effect can be an issue with HiK: Increased coupling between source & extension gate Gate insulator drain in thicker insulator source drain © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 19
  20. 20. 2008 Difficulties in down scaling EOT By courtesy H.Iwai, SC Kyungpook National Univ., Korea, March 2009 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 20
  21. 21. 2008 Metal Workfunctions Φm Tgate eletcrode G Cg-depl. tdepletion Cg-ox tox reduce gate depletion capacitance S Cg-inv. tinversion D Vacuum level Nb 3.99-4.30 1 Al 4.06-4.20 Cg = 1 1 1 Ta 4.12-4.25 qχSi= 4.05eV + + Cg-ox Cg-depl Cg-inv Mo 4.30-4.60 Ec Zr 3.90-4.05 ZrSi2 V 4.12-4.30 ϕmn+(Ei+0.55V) TiSi2 Ti 3.95-4.33 Silicon TaSi2 TaSixNy TaN 4.2-3.9 ϕmn(Ei+0.2V) Co 4.41-5.00 Ru 4.60-4.71 CrSi2 WSixNy Eg=1.12eV Midgap Ei W 4.10-5.20 Rh 4.75-4.98 MoSi2 WCxNy WNx qϕmSi(Ei)=4.61eV Os 4.70-4.83 Au 4.52-4.77 WSi2 ϕmp(Ei-0.2V) TiNx 4.60-4.90 TiSixNy Cr 4.50-4.60 Pd 4.80-5.22 NiSi2 Re 4.72-5.00 CoSi2 Ir 5.00-5.70 ϕmp+(Ei-0.55V) RhSi Pt 5.32-5.50 PdSi Ev RuO2 4.90-5.20 Qox Q Q VFB = Φms − = Φms − ox SMSze Physics of Semiconductor Devices 1981 VT = VFB + 2Φ F − B Cox Cox J.Hauser IEDM 1999 Short Course © CEA 2006. Tous droits réservés. Cox Φ = Φ − Φ Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA MS M s S.Deleonibus, ESSDERC Short Course, September 2009 21
  22. 22. 2008 Damascene Metal gate and HfO2 CMOS wwwww Nitride spacers HfO2 TiN 3 HfO2-NMOS 10 HfO2-PMOS SiO2-NMOS SiO2-PMOS Tungsten 1 Jg @ Ivg-VtI = 1V 10 TiN 10nm -1 10 HfO2 2.20nm (3nm as dep) -3 Amorphous layer 0.90 nm 10 -5 10 LETI, ST: B.Guillaumot et al. Presented IEDM 2002 10 -7 Dec. 10-12, 2002, San Francisco(CA) 1 1,5 2 2,5 3 EOT(nm) © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 22
  23. 23. 2008 HiK & Metal gate Dual gate CMOS -introduction @45nm node -demonstration @32nm node (S.Natarayan et al. IEDM 2008) Gate last(Damascene) process flow Advantages of gate last flow • High Thermal budget available for Midsection – Better Activation of S/D Implants • Low thermal budget for Metal Gate – Large range of Gate Materials available • Significant enhancement of strain – Both NMOS and PMOS benefit Intel: K.Mistry et al, IEDM 2007 K.Kuhn, IEDM 2008 Short Course © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 23
  24. 24. 2008 Main Mobility Enhancement Techniques Substrate-based Process-based SixGe1-x Crystal/Channel Liners SEG Gate MEOL SSOI Bulk SOI CESL SMT eSiGe eSiC Replac. Gate Contact Tensile bi-axial Natural µ enhancement Tensile Tensile Comp. Tensile Tensile Tensile nMOS pMOS nMOS nMOS pMOS nMOS nMOS nMOS +pMOS Compressive Compressive pMOS pMOS <100> (110) SSOI Channel Orient. Substrate Orient. Difficult to manage with FDSOI ultra-thin film © CEA 2006. Tous droits réservés. C.Fenouillet Béranger, 215th ECS Spring 2009, San Francisco Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 24
  25. 25. 2008 Strain and bandgap engineering Compressive strain Tensile strain Tensile strain a= 5.43 Six Ge1-x Si1-y Cy Si Bi-axial Si Si Six Ge1-x pMOS sSi 30nm SiGe Band offset and splitting 5.43<a<5.65 ∆ (2) ∆(4) hh lh ∆ (2) ∆(4) nMOS lh hh ∆(4) ∆(2) hh lh ∆ ∆Ec=-6.5y ∆Ec=0.6x Ev=0.74x Six Ge1-x Si1-y Cy Si Si Si Six Ge1-x Ev Ec Ev Ec Ev Ec In Si Ge C No strain if x=10y Stressors 1-x-y x y (CESL, source & drain, salicide,…) Uni-axial nFET nMOS pMOS L ES c -C Si © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 25
  26. 26. 2008 Strained Si + strained Ge channels -5 3 10 560 universal HfO /TiN electrons (A/µm) 2 V =+/-1.2V -5 D gate stack 2.5 10 x1.65 Mobility (cm2.V-1.s-1) 480 L =10µm G -5 x6 400 s-Ge (holes) 2 10 Dsat W=400µm s-Si Drain Current I 320 s-Si (electrons) -5 s-Ge TiN CVD gate 1.5 10 240 PMOS NMOS Si refs. (electrons) 1 10 -5 160 universal Si holes 5 10 -6 80 Si Si refs.(holes) 0 5 5 5 5 6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 0 2 10 4 10 6 10 8 10 1 10 Effective field (V/cm) Gate overdrive V -V (V) G TH • Improved hole mobility in compressively strained Ge and electron mobility in tensily strained Si • Symmetrical drain current for any dual channel CMOS => tremendous advantage on design layout(WN=WP) LETI,Alliance: O.Weber et al., IEDM, 2005 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 26
  27. 27. 2008 Short channel issues on strained architectures 100 Strained = CESL-sSi Bi axial Low field Mobility gain (%) Devices = sSiGe 80 = sSi 60 +Uniaxial 40 20 0 Bi axial -20 symbols = exp. lines=input for Id model -40 0,01 0,1 1 10 Effective Gate Length (µm) LETI, Alliance, SOITEC: F.Andrieu et al. VLSI Tech. Symp, 2005 ESL-sSi : ⊕ m* reduction ⊕ strain enhancement F.Andrieu et al., ESSDERC 2005 Best paper Award sSiGe : ⊕ m* reduction extra charged defects sSi : quantization effects phonon scattering not dominant © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 27
  28. 28. 2008 Silicon On Insulator Smart-Cut process LETI invention Initialsilicon A B L Oxidation Buried oxide A Smart-Cut H+ ions implant A 5.1016 cm-2 tSi Cleaning and A SiO2 bonding Si B A Smart-Cut splitting at 500°C B Annealing 1100°C CMP touch polishing SOI wafer A Wafer A becomes B New A B © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA LETI : M. Bruel, Elec. Lett., vol. 31, n° 14, p. 1201, 1995 S.Deleonibus, ESSDERC Short Course, September 2009 28
  29. 29. 2008 Electrostatic integrity O.Weber et al, IEDM 2008 300 International Benchmarking F. Bœuf, VLSI 2009 250 EOT~1nm DIBL (mV/V) 200 Bulk Bulk 150 FDSOI 100 FDSOI FinFET (TSOI ~9nm, EOT~1.7nm) 50 FinFET 0 10 20 30 40 Gate Length (nm) Table 1. Characteristic scale length expressions for various thin film device architectures calculated from 2D Poisson equation (from ref. 18-21). No channel doping of thin films Device Surface conduction Volume conduction architecture Scale length Scale length FDSOI devices FDSOI ε Si ε Si  ε t  λ= t Si t ox λ= t Si  t ox + ox Si  single gate ε ox εox   ε Si 2   T.Poiroux, G. Le Carval ε Si t Si ε Si t Si  ε t  in Electronic Device Architectures for the Nano- Double gate λ= t ox λ=  t ox + ox Si  εox 2 ε ox 2   εSi 4  CMOS Era  From Ultimate CMOS Scaling to Beyond CMOS Cylindrical ε Si t Si  t Si  2t ox  ln 1 +  ε ox t Si   λ= + Devices, Editor: S.Deleonibus, Pan Stanford channel εox 4  2    t Si  ε 4  Si  Publishing, Oct 2008 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 29
  30. 30. Improved Figures of Merit from SOI 2008 Lower Power consumption for SRAM 10000 Bulk same standby leakage 125° C @ 1.2V for the memory 1000 SOI cell compared to bulk Isb (pA) 100 @25°C, lower leakage @ 25° C SOI 10 125°C BULK ) 1 0.7 0.9 1.1 Vdd (V) 1.3 1.5 1.7 gain in speed, for same dynamic Power, 1Mb SRAM – Measured access time vs Total 1.5E-08 Power compared to bulk Tacc(Ptot) Tacc = tacc of memory + access to the I/O! 1.4E-08 1.3E-08 BULK SOI 1.2E-08 1.1E-08 but also 30% dynamic Tacc (s) 1.0E-08 9.0E-09 1.2 130nm BULK Power reduction at same 8.0E-09 7.0E-09 130nm SOI 1.2 V speed, compared to bulk ! 6.0E-09 V 5.0E-09 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0.004 LETI: C.Raynaud et al., ECS invited talk , Ptot (W) May 2005 see also J-LPelloie ISSCC 1999 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA PDSOI All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 30
  31. 31. 2008 32nm Low Power FDSOI 2.5nm Strained SOI Bitcell 0.179 m2 Lg=18nm 300mm 6T SRAM NiPt Poly 80nm TiN 10nm Tsi 10nm HfSiON 2.5nm Quasi-ballistic transport enhanced by BOX 145nm confinement & strain -5 ) (A/µm) 2.5nm<t <4nm SI -6 t =5.5nm SI t =8.6nm -7 SI +40% OFF t =11.8nm SI -8 Off current log(I n-SOI -9 L =18nm n-sSOI eff t =11.1nm -10 SI t =9.1nm SI -11 t =6.8nm 0.248 m2 SNM (1.2V)=140mV VDD=1V SI 2.5nm<t <4.5nm SI -12 0.179 m2 SNM (1.2V)=230mV Ioff=6pA/ m 100 200 300 400 500 600 700 800 On current I (µA/µm) ON C.Fenouillet Beranger et al., IEDM 2007 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA V.Barral et al., IEDM2007 S.Deleonibus, ESSDERC Short Course, September 2009 31
  32. 32. 2008 Scalability boosters: TSi LETI, SOITEC: Weber et al. , IEDM2008 120 300 Symb. : Experiment L = 20nm International Benchmarking g 100 Model 250 EOT~1nm DIBL (mV/V) L =30nm g DIBL (mV/V) 80 200 Bulk L =40nm g 60 150 40 L =80nm 100 FDSOI g (TSOI ~9nm, EOT~1.7nm) FinFET 20 50 L =120nm g 0 0 2 4 6 8 10 12 Si film thickness t (nm) 10 20 30 40 SI Gate Length (nm) Thinning TSi is effective to reduce SCE and DIBL High electrostatic integrity in planar FDSOI vs. Bulk and FinFETs © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 32
  33. 33. 2008 Variability : LER, OTF, RD -random dopants fluctuations major issue @ nodes<45nm adds to LER and OTF VT and circuit behaviour -superiority of thin film on bulk A.Asenov, Tech Dig. VLSI Tech Symposium, p.86, Kyoto 2007 © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 33
  34. 34. 2008 Record-high VT matching perf. 3 120 Bulk platform ST 65nm σ∆Vt=34.5mV planar FDSOI [11] 2.5 ST 45nm 100 [10] IBM 90nm [9] σVt=24.5mV A (mV.um) 80 Intel 65nm Count AVt=0.95mV.µm 2 IBM alliance 32nm [3] [7] 60 W=60nm Intel 45nm Vt L=25nm 1.5 40 UTBSOI 1 LETI [1] 20 square : V =50mV d circle: V =1V d 0 0.5 7 9 3 5 1 5 10 20 30 40 50 60 15 33 51 69 87 5 0 -8 -6 -5 -3 -1 10 0 -1 Vt shift ∆Vt (mV) Gate length L (nm) O.Weber et al., IEDM 2008 (σVt=σ∆Vt/√2 to compare measurements on pairs and on arrays of transistors in the literature) Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs © CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA S.Deleonibus, ESSDERC Short Course, September 2009 34

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