Thermo-Mechanical Simulation of Through Silicon Stack Assembly

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The electronics industry has been using Finite Element Analysis (FEA) to model IC package assembly process for understanding the effects of process conditions, material choice as well as design parameters. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for streamlined methodologies and information exchange protocols.

This presentation will introduce the idea of automated chip stacking process modeling approach with detailed discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance. The presentation will discuss wafer level warpage due to thinning and RDL films, their control, assembly implications of different under filling and encapsulation processes and pre attach warpage at reflow temperature

Published in: Design

Thermo-Mechanical Simulation of Through Silicon Stack Assembly

  1. 1. Thermo-Mechanical Simulation ofThrough Silicon Stack Assembly Kamal Karimanal Cielution LLC www.cielution.com © Cielution LLC
  2. 2. Agenda Classification of 3D Through Silicon Stacking – Modeling Case Study  Effect of chip attach sequence and underfilling on Stack warpage & Package Yield Gaps in Thermo-Mechanical Modeling Supply Chain – Characterization (Underfill focus) – Automation FEA of Chip Stacking flows Solutions to Modeling Automation © Cielution LLC
  3. 3. Traditional Flip Chip Process StepsStep I: Silicon, solder bump and substratebond at reflow temperature (~230 C) 400 to 800 um die Step II: Cool down from 230 C to room temperature Step III: Underfilling, cure at 150 C, Cool to room temperature Step IV: Lid attach/encapsulation at ~120C, cool down to room temp Step V: Ball attach & reflow at ~ 230C,
  4. 4. 3D Assembly Flow I: D2D, Chip Stack First, CUFStep 1: Mem Stack to Logic Step 2: Capillary Underfill Step 3: Chip Stack to Substrate(@ reflow Temperature 230 C) (@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 5: Overmolding or Lid Attach © Cielution LLC
  5. 5. 3D Assembly Flow II: D2D, Chip Stack First, NUF & CUFStep 1: Mem Stack to Logic Step 2: No Flow Underfill Step 3: Chip Stack to Substrate(@ reflow Temperature 230 C) (@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 5: Overmolding or Lid Attach © Cielution LLC
  6. 6. Other Variations Wafer Thinning Carrier Wafer Wafer to be Thinned Wafer to Wafer (W2W) Singulation Chip Stack Follow one of the 3D Assembly Flows © Cielution LLC
  7. 7. Other Variations Wafer Thinning Carrier Wafer Wafer to be Thinned Die to Wafer (D2W) Bonding Thinned Wafer Carrier WaferOptions?Wafer Level Underfilling? Carrier Removal Followed by SingulationEncapsulation? Follow one of the 3D Assembly Flows © Cielution LLC
  8. 8. Options for Chip to Chip Attach Micro Bumps Copper Pillar Copper Nails + Thermo Compression © Cielution LLC
  9. 9. Underfilling Options No Flow Underfill Capillary Underfill (CUF) Copper Nails + Thermo CompressionMolded Underfill (Vaccuum Assist) No Need to Underfill © Cielution LLC
  10. 10. Summary of Through Silicon Stacking Unit Processes From Process Flow Perspective – W2W Vs. D2W Vs. D2D – Chip Stacking First Vs. Chip 2 Substrate First  Reference: Minsuk Suh, Semetech Symposium http://www.sematech.org/meetings/archives/symposia/10350/pres/Session_05_01_Suh_Final.pdf) From an Underfilling Perspective… – Capillary Underfilling (CUF) – No Flow Underfilling (NUF) – Molded Underfilling (MUF) Bonding Perspective – Reflow @ 230 C – Thermo-compression Bonding @ 300-400 C © Cielution LLC
  11. 11. Thermo Mechanical Challenges that are influenced by Unit Processes Warpage – Thinned Wafer/Chip Warpage at attach temperature  Assembly yield Risk – Stack Warpage at Room Temperature  Chip Cracking Risk Bump and underfill level Stresses  “whitebump” Risk  Underfil Delamination Risk © Cielution LLC
  12. 12. Warpage – A major Assemby Challenge Thinned Wafer/chip Warpage Estimation R, radius of curvature Techniques Film Stress, – FEA Simulation – Stoney Equation tf  50 um thick silicon is tSi not much thicker than the Front and Back 2 Side RDL Films (~5 to ESi t si 1 Stoney s Formula f 10 um each). Validity tf R of Stoney equation is questionable. © Cielution LLC
  13. 13. Modeling Methodology © Cielution LLC
  14. 14. Model Flow for Chip 2 Chip Build Geometry below – Existing Geometry engine with minor modification for films – Detailed TSVs will not be included in the model for simplicity Mesh this Geometry – Should mesh automatically based on the existing thermal methodology
  15. 15. Model Flow for Chip 2 Chip Ekilled parts Step 1: – Ekill Mold Compound, all Stacked Chips, bump regions, and one side film if ref temperature is different. – Start Temperature is reference temperature of the film and the main chip  T(t=0) = T1 – End temperature is the reference The effectively remaining geometry temperature of the second film  T(t=1) = T2
  16. 16. Model Flow Chip 2 Chip Step 3.1.1: Step 2: • Ealive Second film of second chip at T4 • Ramp to T5 • Ealive Second Film at T2 •(T5 is the bump reflow temperature for attach between Chip 1 & Chip 2) • Ramp to T3 • (T3 is the reference temperature of Steps 3.2 & 3.2.1: the first film on Chip 2) Step 3.1: • Repeat Steps 3.1 & 3.1.1 for other chips on Chip 1 (use respective T3 & T4) Step 4:• Ealive Second chip with one film at T3• Ramp to T4 • (T4 is the reference temperature of the second film on Chip 2) • Ealive Lumped Bumps* of all Chip1–Chip_x interfaces at T5 • Ramp to T6 •(T6 is the underfill Cure temperature for the interface)
  17. 17. Chip Stacking Case Study © Cielution LLC
  18. 18. Stack up Description Logic Die (23mmX16mm) SubstrateFSRDL Films BSRDL Films 4X4 Memory Memory Chips Stacks (10X6.5) Underfill Regions Logic Die © Cielution LLC
  19. 19. Assembly Flow I: D2D, Chip Stack First, CUFStep 1: Mem Stack to Logic Step 2: Capillary Underfill Step 3: Chip Stack to Substrate(@ reflow Temperature 230 C) (@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 5: Overmolding © Cielution LLC
  20. 20. Flow I Chip Stack warpage on attach+underfill &Cool down T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered © Cielution LLC
  21. 21. Flow I substrate warpage on attach to Chip Stack &Cool down T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered © Cielution LLC
  22. 22. Flow I & Flow II substrate warpage on attach to Chipstack, overmolding & Cool down T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered © Cielution LLC
  23. 23. Flow I Consolidated Room Temperature Warpage Evolution T=20 Deg Title Chart C results500400300200100 0 0 5000 10000 15000 20000 25000 30000 35000 40000-100 Logic_die_warpage_after_stack_attach Substrate_warpage_after_stack_attach Sub_warpage_after_full_assembly © Cielution LLC
  24. 24. Realistic Factors Influencing Warpage @ Attach R, radius of curvature  Material choice for RDL, underfill, encapsulation etc., – Affects CTE, Modulus Film Stress,  Intrinsic Stress in RDL films tf – Affected by process temperature tSi  Chip Attach Temperature f Th erma l In trin sic E TD T E Tv TD E Tv T  # of Metal layers in RDL & their f 1 1 1 mismatch between front and back side 2 t si 1 ESi Stoney s Formula f tf R  Process difference between Besser, Paul R.; Zhai, Charlie, “STRESS-INDUCED different IC stacks PHENOMENA IN METALLIZATION: Seventh International Workshop on Stress-Induced – For Example, Memory Cube using Phenomena in Metallization. AIP Conference Proceedings, Volume 741, pp. 207-216 (2004).” Thermocompression Bond, C4 using traditional reflow + CUF24 December 5, 2012
  25. 25. Assembly Flow II: D2D, Substrate Stack First, CUFStep 1: Mem Stack to Logic Step 2: Capillary Underfill Step 3: Memory Stack Attach(@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 5: Overmolding © Cielution LLC
  26. 26. Flow II substrate warpage on attach+underfill to thinned logic & Cool down T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered 500Substrate 1st: Thinned Die onSubstrate 400 300 200Chip Stack 1st: Stacked Chip on 100Substrate 0 0 5000 10000 15000 20000 25000 30000 35000 40000 -100 sub+thinned_die_warpage_Rt sub+chip_stac_Rt © Cielution LLC
  27. 27. The warpage that Really matters for Assembly… We have been seeing Room temperature warpage for various scenarios. There were no physical reasons for warpage at attach temperature: – By using same thickness films – Films were considered stress free at attach temperature. – This is rarely the case when different IC stacks come from different sources For example let’s take the case of memory cube stacked using Thermocompression… © Cielution LLC
  28. 28. Combo Assembly Flow IV: W2W TC for mem cube, reflow + CUF for Logic Attaches Step 1: Memory Stack from Step 2: Mem Stack to Logic with Step 3: Capillary Underfill W2W Thermocompression @ PI RDL (@ reflow Temperature (400 C) Oxide RDLs 230 C)Step 4: Chip Stack to Substrate Step 6: Overmolding(@ reflow Temperature 230 C) Step 5: Capillary Underfill © Cielution LLC
  29. 29. Chip stack warpage at Substrate attach temperature Logic die & Underfill stress free at Reflow Temperature Memory Cubes stress free at 400CPeak to Valley of 137 micron’smean that the stack cannot beassembled without force © Cielution LLC
  30. 30. Comparison of stress distribution across StackAll ReflowThermocompression for MemoryStack + reflow for other attachment © Cielution LLC
  31. 31. What does this mean to the supply chain? Foundry: Wafer & Chip Stack Yield Learning  Test Chip Program ~ 1+ years  Modeling assessment of RDL, bumping & Bonding options: Weeks OSAT: Assembly Yield Learning & Supplier Readiness – Fully Assembled Test Vehicle ~ 1+ years – Modeling assessment of feasibility ~ Weeks Fabless Customer: 3D stack technology choice Vs Product roadmap – Qual vehicles ~ 2Q+ – Modeling assessment of Feasibility ~ Weeks Thus, Thermo-Mechanical modeling can offer some learning quickly. – But needs to provide comparable metrics.  To be able to estimate risk in comparison with knowns. – Thermo-Mechanical Model Supply Chain Gaps? © Cielution LLC
  32. 32. Thermo-Mechanical Model Supply Chain Gaps? Materials Characterization Park & Feger 9 ECTC, 2008 Characterization Relaxation Modulus(GPa) 8 7 – Materials Tg 6 5 – Failure Metrics & Criteria 4 5 sec 3 2 120 Sec 1 0 Underfill Characterization 0 50 100 150 200 Temperature (Deg C) needs: – Non Linear Material Properties Huang et al., Electronic  Modulus, CTE, Materials & Packaging, 2002 Poisson’s Ratio Tg – Temperature dependence – Viscoelasticity? © Cielution LLC
  33. 33. Underfill Material Characterization Needs Mechanical Simulation Needs: – Modulus & CTE as a function of Temperature  Or, at least 1 value well above Tg & 1 Value well below Tg – Glassification Temperature (Tg) – Poisson’s Ratio Thermal Simulation Needs – Conductivity – Specific Heat – Density © Cielution LLC
  34. 34. Thermo-Mechanical Model Supply Chain Gaps? Gap # 1: Automation Why – There can be close to 100 input parameters defining a process flow – Manual Modeling by direct input to solver engine can be lead to errors – Hence the need for automation © Cielution LLC
  35. 35. Who is Cielution?How do we Address Simulation Automation Needs? © Cielution LLC
  36. 36. Who is Cielution?
  37. 37. Cielution Services Expertise Areas • Thermal and Mechanical Simulation • Chip, Package Board and System Level Engineering. Tools Expertise • ANSYS, Icepak, Fluent, CFX, Flotherm Business Model • Fixed Cost Fixed Time Projects • Hourly rate & Temporary Resources
  38. 38. Cielution Product Pipeline CielSpot™ CielMech™ – – Package Thermal Modeling Package Compact Model • Thermo-Mechanical Generation Analysis of Assembly CielSpot-CTM™ o Warpage Mitigation – Thermally Aware IC Layout o Packaging Yield  Traditional Packages Enhancement  3D Stacked Assemblies o Interconnect Reliability
  39. 39. CielMech™ & CielSpot™ for Modeling Automation © Cielution LLC
  40. 40. CielMech: High Level Workflow Stack InfoPackage CielMech™ Process InfoInfo Automated Geometry, Meshing & Problem Setup Automated Reports, Images & custom Post Processing Intelligent Solver Controls Solve in Commercial FEA Tool Access to Model in the commercial solver’s native format © Cielution LLC
  41. 41. CielSpot for Thermal IC Package Detailed & Compact Thermal Modeling © Cielution LLC
  42. 42. CielSpot Usage: Direct Solve Direct Solve Access to Model in the commercial Solver’s Native Format Stack InfoPackage CielSpot CommercialInfo Thermal Solver Power Map Info Automated Thermal Snapshots & Temperature data © Cielution LLC
  43. 43. CielSpot Usage: Compact Model Generation For IC Design & Layout Access to Model in the commercial Solver’s Native Format Stack InfoPackage Pre-Characterization CielSpot using CommercialInfo Thermal Solver Compact Thermal Model © Cielution LLC
  44. 44. CielSpot Usage: Compact for Fast Solve Without CFD/FEA Pmap for Chip 1 Pmap for Chip 2 Pmap for Chip 2 … Etc…Input Data CielSpot Pre-characterization CielSpot CTM Automated Thermal Snapshots & Temperature data © Cielution LLC
  45. 45. Summary & Conclusions 3D Stack Assembly Flow, bumping, Underfill & Attach Strategy lead to coupled thermo mechanical Scenarios – Affects Stack warpage, Assembly Yield and Package Reliability Automated Thermo Mechanical Simulation along with Collaborative strategy can help understand risk prior to technology commitment Sneak Peaked at modeling automation tools in pipeline – Thermo Mechanical modeling Automation CielMech™ – Thermally aware chip and IC layout process automation  Direct numerical solution using CielSpot™  Compact Modeling Approach using CielSpot™ + CielSpot CTM ™ © Cielution LLC
  46. 46. Author Contact: Kamal KarimanalCielution LLC (www.cielution.com) kamal@cielution.com Phone: 408 898 2435 © Cielution LLC

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