The electronics industry has been using Finite Element Analysis (FEA) to model IC package assembly process for understanding the effects of process conditions, material choice as well as design parameters. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for streamlined methodologies and information exchange protocols.
This presentation will introduce the idea of automated chip stacking process modeling approach with detailed discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance. The presentation will discuss wafer level warpage due to thinning and RDL films, their control, assembly implications of different under filling and encapsulation processes and pre attach warpage at reflow temperature