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- 2. MEHRAN UNIVERSITY OF ENGINEERING & TECHNOLOGY JAMSHORO ACHIEVING HIGH INPUT POWER FACTOR FOR DCM BUCK CONVERTER BY VARIABLE DUTY CYCLE CONTROL MUHAMMAD OSAMA NIZAMANI (17 ME ELP 19) SUPERVISOR: DR. ABDUL HAKEEM MEMON CO-SUPERVISOR: PROF. DR. ZUBAIR AHMED MEMON 2
- 3. 3 Contents Introduction Literature Review Problem Statement Research Objectives Research Methodology Operating Principle of DCM Buck PFC Converter Variable Duty Cycle Control Scheme to Improve PF Fitting Duty Cycle Implementation of Control circuit Compression Analysis between CDCC and VDCC Simulation verification Conclusion Future work References
- 4. AC/DC power conversion is an important research area of power electronics technology. Harmonic pollution caused by increased number of electronic appliances has become a serious issue To meet the international harmonic standards, e.g. IEC 61000-3-2 limit power factor correction (PFC) converters had developed and adopted in the power systems, which can attain low harmonic distortion and high power factor (PF). Introduction 4
- 5. Introduction (cont.) There are variety of topologies and control schemes to achieve PFC. The buck converter is one of the commonly used topology, especially in low power applications due to its advantages of low voltages stress on semiconductor switch, low dc output voltage, small conduction losses, low inrush current. As compared to other PFC converters, buck converter can achieved high efficiency in entire universal input voltage range. 5
- 6. Hadley (1989) offer a solution where by controlling the pulse width modulation gradient through ac module of the rectified input voltage a variable duty cycle could be achieved. Though, smallest current alteration gained by this strategy is around about 10%, so additional change promotes near unwanted increase in fifth or seventh harmonic component [1]. D. Weng (1996) introduce solution, in which the operating system in controlled by second harmonic of reference voltage. That technique needs complicate and expansive additional circuitry, for example phase-locking-loop and phase-detecting but that is very effective for distortion reduction [2]. schramm (1998) proposed peak current control in which with constant duty cycle a given harmonic which is inserted to the assumed current for eliminating the third harmonic to reference current and the power factor could be enhanced near unity [3]. Literature Review 6
- 7. Huber et al (2010) introduce design-oriented analysis, a significant optimization and execution assessment on clamped current buck PFC converter [4]. Kai Yao (2011) apply a variable duty cycle control on DCM boost PFC converter to improve PF [5]. Wu et al (2012) present a variable on-time regulator into CRM mode buck PFC converter in high- illumination LED application to meet the lighting system limitation and for current harmonic reduction [6]. X. Xie et al (2013) put forward to eliminate the dead zone of buck converter he added two diodes and an auxiliary switch [7]. D.D.-C. Lu (2013) evaluates a example of buck PFC and buck-boost dc/dc single step stage converter and put forward a scheme of a low load power loss of reduction [8]. Literature Review ( Cont.) 7
- 8. Ohnuma (2014) adopt a small capacitor with active buffer for power decoupling in a buck PFC and achieves a low output voltage ripple and high PF [9]. kai Yao (2017) propose for improvement of PF by optimizing third harmonic. By compared with sinusoidal current control the planned switch technique gains a large PF and minor output voltage ripple in the worldwide input voltage choice [10]. A. Hakeem Memon (2017) introduce a variable-on-time (VOT) control scheme designed for CRM integrated buck and flyback PFC converter with high power factor (PF) and low total harmonic distortion (THD). By utilizing input and output voltage to modulate the on-time of both buck and flyback switches, the input current harmonic can be eliminated and high PF will be obtained [11]. Literature Review ( cont.) 8
- 9. A. Hakeem Memon (2018) propose an approach of unity PF control (UPC) for boundary conduction mode (BCM) buck-buck/boost PFC. The control framework can secure high power factor and low total harmonic distortion by applying input/output voltages to modulate the on-time of both buck and buck/boost switches [12]. A. Hakeem Memon (2018) proposed variable-on-time (VOT) control scheme for CRM buck- buck/boost converter to realize high input PF [13]. Memon et al., (2019) has introduce flyback converter to work with Buck converter for boundary condition mode (BCM) to improve PF. [14] Literature Review ( cont.) 9
- 10. Literature Review ( cont.) Memon et al., (2019) has introduce buck/boost converter to work with buck converter for (BCM) buck converter to improve PF. [15] Memon et al., (2019) has proposed control technique to improve input PF of integrated buck- flyback converter. [16] 10
- 11. “A buck PFC converter is widely used in low-power application for its many applications. However, when duty cycle is kept constant in a line cycle, the average input current is not proportional to the input voltage, so PF is not high and also because of the inherent dead zone as shown in figure 1, the input PF is not high. Therefore, it is essential for the buck converter to improve its PF, so that its average input current can meet IEC limit” Problem Statement 11
- 12. 12 Figure 2
- 13. Research Objectives To propose variable duty cycle control scheme to improve Power Factor (PF). To develop simulation model by using saber simulator to verify the effectiveness of VDCC for DCM Buck PFC converter. 13
- 14. 1 • Literature survey along with collection of books and equipment’s. 2 • Input PF analysis of tradition DCM buck converter. 3 • Introduction to variable duty-cycle control to improve the input PF. 4 • Fitting duty-cycle by using Taylor’s series. Research Methodology 14
- 15. 5 • Implementation of proposed control scheme. 6 • Comparison analysis between two control schemes in terms of input PF. 7 • To develop simulation model by using Saber Simulator of DCM buck PFC converter for constant duty cycle control (CDCC) and variable duty cycle control (VDCC) 8 • Verifying result 9 • Thesis write up Research Methodology ( cont.) 15
- 16. Operating Principle of DCM Buck PFC Converter D1 D2 D3 D4 vin iin EMI Filter Co Lb Qb Dfw Vo RLd Schematic diagram of a DCM buck PFC converter Figure 2 16
- 17. Operating Principle (cont.) The instantaneous and rectified input voltage during half line cycle can given as sin in g m v v V The input current of Buck converter is given as 2 0 0 ( sin ) 2 m o y in b s V V D i L f Equations are derived in details in research paper and thesis (1) (2) 17
- 18. The input PF of Buck converter is given as 0 0 2 _ 2 sin ( sin 1) 1 ( sin 1) 2 o o in m in rms a d P PF V I a d The input power with CDCC of Buck converter is given as 0 2 /2 0 1 sin (V sin ) / 2 2 line o T m y in in in m o line b s V D P v i dt V d T L f Vm =Input voltage amplitude θ = input voltage angular frequency Dy =Duty cycle (3) (4) 18 Operating Principle (cont.)
- 19. PF Vm/Vo 2.766 3.111 3.457 3.803 4.148 0.970 0.975 0.980 0.985 0.990 Relation between the input PF and Vm/Vo Vo=Voltage output a= Vm/Vo Figure 3 19 Operating Principle (cont.)
- 20. Variable Duty Cycle Control Scheme to Improve Input PF For achieving unity PF , the variation rule for duty cycle is 0 0 0 sin sin m y m o D V D V V where Do is a co-efficient By replacing the value of Dy in (2), we can get 0 0 0 sin 2 m in b s D V i L f Above equation shows that input current is pure sinusoidal and hence unity PF can be achieved (5) (6) 20
- 21. Variable Duty Cycle (cont.) The average input power with proposed control scheme is given as 0 0 0 sin 1 sin 2 s m in m o b D TV P V d P L D0 can be obtained as 0 2 0 0 4 V 2 sin 2 b s o m L f P D 0 0 0 0 4 sin V 2 sin 2 sin o b s y m m o P L f D V V (9) (8) (7) 21
- 22. Fitting Duty Cycle The subtraction, multiplication, division and root operation included, the duty-cycle expressed in (9) is complicated to be realized by analog circuit. Therefore, it is necessary to simplify (9). Defining a=Vm/Vo, y=sinθ, (5) can be rewritten ass 0 0 0 a 1 y D ay D y (10) Talyor’s series 2 ' '' 0 0 0 0 0 0 0 1 1 2! ! n n f x f x f x x x f x x x f x x x n (11) 22
- 23. By using Talyor’s series the simplified equation is 0 0 0 _ 1 0 0 2 2 0 0 0 0 0 0 2 1 1 (1 ) 1 2( 1) 2 2 y fit D ay ay y y D D ay ay ay y ay y Where 0 0 0 1 0 0 2 1 1 2( 1) D ay ay D ay ay (12) Therefore the input current and input Power for VDCC 2 2 1 2 0 0 _ 0 0 ( sin 1)(1 ) 2 2 o in VDCC b s y V D a ay y i L f (13) 23 Fitting Duty Cycle (cont.)
- 24. 0 2 2 1 _ 2 0 0 sin sin ( sin 1)(1 ) 2 2 o m o in VDCC o b s V V D P P a d L f ay y (14) From (13) and (14), input PF is calculated as 0 0 0 2 2 0 0 2 4 2 _ _ 0 0 2 sin (2 sin ) ( sin 1) (2 sin ) ( sin 1) o in in rms in rms ay y a d P PF V I ay y a d (15) If input voltage range is 176-220 VAC output voltage is 90 V replacing a= into (15), and differentiating (15) with y0, also setting it to zero, y0=0.75 is obtain 176 2 / 90 _ 1 0 0 1.125 0.75 sin 1.125 0.75 m o o y fit m o V V V D D V V (16) 24 Fitting Duty Cycle (cont.)
- 25. Implementation of the Control Circuit C vEA x y z v v v vx vy vz R7 vo R5 R6 R8 + _ + _ R15 R16 R17 C2 Vog vof + _ + _ 2 1 9 R S Clock PWM Latch Frequency Divider Comp E/A Qb 11 14 D2 D3 UC3525A P D R9 R10 R13 R14 + _ A + _ vg R1 R2 vgf D R11 A of B v v v R3 D1 Feedforward Circuit Multiplier Multiplier Error Amplifier + _ B C1 R4 0.75 1.125 sin 0.75 1.125 o m o P EA o m V V V v v V V Figure 4. Control circuit of the variable duty cycle control 25 (17)
- 26. Comparison Analysis Between CDCC and VDCC From (4) and (15), the input PF curves with a CDCC and a VDCC are drawn and shown in figure 5. it can be observed that VDCC improve the input PF. Once the input voltage is set at 176 VAC, the PF is improved from 0.971 to 0.983. constant duty cycle control variable duty cycle control 176 198 220 242 264 Vm / 2 0.96 0.97 0.98 0.99 1.00 0.971 0.983 FIGURE 5 26
- 27. Simulation Verification For verifying the effectiveness of VDCC strategy, simulations are carried out. The input voltage range is 176-264 VAC and the output voltage is 90 V. for ensuring the current to be in DCM, UC3525A IC is used. Figures show the simulation waveforms of vin, iin, and vo of buck converter with CDCC and VDCC at 176-264 VAC inputs, respectively. It can be observed that the input current with VDCC is more sinusoidal as compared with CDCC. 27
- 28. v o /V v in /V i in /A 80 95 -1.5 1.5 0 400 0 90 90 Figure 6. vin, iin, and vo with CDCC on 176 VAC v o /V v in /V i in /A 80 95 -1.5 1.5 0 400 0 90 90 Figure 7. vin, iin, and vo with VDCC on 176 VAC 28 Simulation Verification
- 29. v o /V v in /V i in /A 80 95 -1.5 1.5 0 400 0 90 90 Figure 8. vin, iin, and vo with CDCC on 220 VAC v o /V v in /V i in /A 80 95 -1.5 1.5 0 400 0 90 90 Figure 9. vin, iin, and vo with VDCC on 220 VAC 29 Simulation Verification
- 30. v o /V v in /V i in /A 80 95 -1.5 1.5 0 400 0 90 90 Figure 10. vin, iin, and vo with CDCC on 264 VAC v o /V v in /V i in /A 80 95 -1.5 1.5 0 400 0 90 90 Figure 11. vin, iin, and vo with VDCC on 264 VAC 30 Simulation Verification
- 31. 31 Conclusion When the duty cycle is kept constant in a line cycle, the average input current is not proportional to the input voltage, so the input PF is not high. In order to improve the PF to near unity over whole input voltage range, a variable duty cycle control scheme is proposed and furthermore a method of fitting the duty cycle has been proposed for simplifying the circuit implementation.
- 32. 32 Future Work 1. Hardware implementation can be achieved for design model. 2. Digital circuit can be used for proposed model in place of analog circuit. 3. Design model can be employed for 3-phase system
- 33. 33
- 34. [1]. Liu, K. H., & Lin, Y. L. (1989, June). Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters. In Power Electronics Specialists Conference, 1989. PESC'89 Record., 20th Annual IEEE (pp. 825-829). IEEE. [2]. Weng, D., & Yuvarajan, S. (1995, March). Constant-switching-frequency AC-DC converter using second-harmonic-injected PWM. In Applied Power Electronics Conference and Exposition, 1995. APEC'95. Conference Proceedings 1995., Tenth Annual (Vol. 2, pp. 642-646). IEEE. [3]. Schramm, D. S., & Buss, M. O. (1998, May). Mathematical analysis of a new harmonic cancellation technique of the input line current in DICM boost converters. In Power Electronics Specialists Conference, 1998. PESC 98 Record. 29th Annual IEEE (Vol. 2, pp. 1337-1343). IEEE. References 34
- 35. [4]. Huber, L., Gang, L., & Jovanovic, M. M. (2010). Design-oriented analysis and performance evaluation of buck PFC front end. IEEE Transactions on Power Electronics, 25(1), 85-94. [5] Yao, K., Ruan, X., Mao, X., & Ye, Z. (2010). Variable-duty-cycle control to achieve high input power factor for DCM boost PFC converter. IEEE Transactions on Industrial Electronics, 58(5), 1856-1865. [6]. Wu, X., Yang, J., Zhang, J., & Qian, Z. (2012). Variable on-time (VOT)-controlled critical conduction mode buck PFC converter for high-input AC/DC HB-LED lighting applications. IEEE Transactions on power Electronics, 27(11), 4530-4539. [7]. Xie, X., Zhao, C., Zheng, L., & Liu, S. (2013). An improved buck PFC converter with high power factor. IEEE Transactions on power electronics, 28(5), 2277-2284. [8]. Lu, D. D., & Ki, S. K. (2013). Light-load efficiency improvement in buck-derived single-stage single-switch PFC converters. IEEE transactions on power electronics, 28(5), 2105-2110. References 35
- 36. [9]. Ohnuma, Y., & Itoh, J. I. (2014). A novel single-phase buck PFC AC–DC converter with power decoupling capability using an active buffer. IEEE Transactions on Industry Applications, 50(3), 1905- 1914. [10]. Yao, K., Zhou, X., Yang, F., Yang, S., Cao, C., & Mao, C. (2017). Optimum Third Current Harmonic During Nondead Zone and Its Control Implementation to Improve PF for DCM Buck PFC Converter. IEEE Transactions on Power Electronics, 32(12), 9238-9248. [11]. Memon, A. H., Yao, K., Chen, Q., Guo, J., & Hu, W. (2017). Variable-on-time control to achieve high input power factor for a CRM-integrated buck–flyback PFC converter. IEEE Trans. Power Electron, 32(7). References 36
- 37. [12]. Memon, A. H., & Yao, K. (2018). UPC strategy and implementation for buck– buck/boost PF correction converter. IET Power Electronics, 11(5), 884-894 [13]. Memon, A. H., Baloach, M. H., Sahito, A. A., Soomro, A. M., & Memon, Z. A. (2018). Achieving High Input PF for CRM Buck-Buck/Boost PFC Converter. IEEE Access, 6, 79082-79093. [14]. Memon, A. H., Pathan, A. A., Kumar, M., Sahito, A. A J., & Memon, Z. A (2019). Integrated buck-flyback converter with simple structure and unity power factor. Indian Journal of Science and Technology, 12(17), 1-5 References 37
- 38. References [15]. Memon, A. H., Memon, Z. A., Shaikh, N. N., Sahito, A. A & Hashmani, A. A (2019). Boundary conduction mode modified buck converter with low input current total harmonic distortion. Indian Journal of Science and Technology, 12(17), 1-5 [16] Memon, A. H., Memon, Z. A., Shaikh, N. N., Sahito, A. A & Hashmani, A. A (2019). buck- buck/boost converter with high input power factor and non-floating output voltage. International Journal of Computer Science and Network Security, 19(4), 1-5 38
- 39. Thank You 39
- 40. Relation between PF and THD 2 1 1 PF THD 2 1 1 THD PF 40