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The vlsi architecture of a highly efficient deblocking filter for hevc systems

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The vlsi architecture of a highly efficient deblocking filter for hevc systems The vlsi architecture of a highly efficient deblocking filter for hevc systems The vlsi architecture of a highly efficient deblocking filter for hevc systems The vlsi architecture of a highly efficient deblocking filter for hevc systems The vlsi architecture of a highly efficient deblocking filter for hevc systems The vlsi architecture of a highly efficient deblocking filter for hevc systems

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The vlsi architecture of a highly efficient deblocking filter for hevc systems

  1. 1. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems Abstract: This paper presents the VLSI architecture and hardware implementation of a highly efficient Deblocking Filter for High Efficiency Video Coding (HEVC) systems. In order to reduce the number of data accesses and thus to enhance the timing efficiency, novel data structures and memory access schemes for image pixels are proposed. Furthermore, a novel edge-fetching order is presented to strike a balance between the processing throughput and complexity. Based on the proposed structure and access pattern, a six-stage pipelined, two-line Deblocking Filter engine with low-latency data access sequence is designed, aiming to achieve high processing throughput while at the same time maintaining low complexity. The detailed storage structure and data access scheme are illustrated and VLSI architecture for the Deblocking Filter engine is depicted in this paper. In addition, the proposed Deblocking Filter is implemented using TSMC 90nm standard cell library. Experimental results based on post-layout estimations show that the proposed design can achieve 60 frames per second for frame resolution of 4096×2048 pixels (Ultra HD resolution) assuming an operating frequency of 100MHz. Moreover, this design occupies area complexity of 466.5 kGE with power consumption of 26.26 mW. In comparison with prior arts targeting on similar system specification and throughput, the proposed design results in a significantly reduced area complexity.The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Existing System: Over the past decades, one of the prominent trends for digital video system lies in the greatly increased resolution such as the High Definition (HD ; 1920×1080) and Ultra HD (409×2048 or 7680×4320) formats. Furthermore, there has been huge demands for accessing digital video contents through wireless signals and/or high-speed transmission interfaces. Therefore, it is paramount to have an efficient video coding (compression) methodology that can significantly reduce the amount of data while at the same time largely maintaining the visual quality.
  2. 2. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Moreover, this methodology needs to be practically realized so that real-time processing can be achieved with manageable hardware complexity. Recently, the latest video coding standard, High Efficiency Video Coding (HEVC), has been established. It is claimed that the HEVC can reach the same visual quality as its predecessor, H.264/AVC, with halved bit rate. This improvement in coding efficiency of HEVC is mainly due to the introduction of more adaptive and flexible basic coding units. Unlike H.264 standard where each frame is divided into 16×16 Macro Blocks (MB), the basic processing unit in HEVC is the Coding Unit (CU) and its size could be from 8×8 to 64×64. Disadvantages:  high-latency data access  low processing throughput Proposed System: This paper presents the VLSI architecture and the hardware implement of a highly efficient Deblocking Filter for HEVC systems. In particular, Inspired by the concept of the “Unified Cross Unit” mentioned, the proposed Deblocking filtering operation is based on novel memory structures and data access patterns so that the number of required memory accesses is reduced and the timing efficiency for data accesses is enhanced. Furthermore, a novel edge-fetching order is presented to strike a balance between the processing throughput and complexity. In order to achieve high throughput with low complexity, based on the proposed structure and access pattern, a six-stage pipelined, two-line Deblocking Filter engine with low-latency data access sequence is designed. Instead of using four-line filter, this design can still process the resolution of 4096×2048 at 60 fps with a much simplified two-line filter, mainly due to the proposed efficient data access scheme. The circuit implementation of the proposed design is clearly illustrated and the experimental results based on post layout estimations are presented. Specifically, four sets of video sequences were sent to the post-layout netlist for verifying the functionality. Moreover, detailed performance analyses and comparisons with prior arts are given in order to shed more lights on the trade-offs between different design considerations. We
  3. 3. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back show that, compared to the prior arts targeting on similar system specification and throughput, the proposed design results in a significantly reduced area complexity. In short, main contributions of this paper can be summarized as follows. 1. Novel memory structures and data access schemes for image pixels are presented. The proposed methodology can reduce the number of memory accesses and enhance timing efficiency for reading and processing image pixels. 2. A novel edge-fetching order is illustrated to strike a balance between the processing throughput and complexity. 3. Based on the proposed memory structure and data access scheme, a six-stage pipelined, two-line Deblocking Filter targeting is designed and implemented. When targeting on the resolution of 4096×2048, this design can achieve 60fps with low complexity. Deblocking Filter In the HEVC standard, each frame is divided into Coding Tree Units (CTU) with sizes of 64×64, 32×32, or 16×16 and, using quad-tree structure, a CTU can be further divided into Coding Units (CU) with sizes from 64×64 to 8×8. The CU is the basic processing unit for intra/inter coding where the largest possible CU size, i.e., 64×64, is known as the Largest CU (LCU). We first present the high-level architectural overview of the proposed DBF system, followed by detailed introductions of each block. Figure 1 presents the high-level architectural overview of the proposed Deblocking Filter along with the re-organization flow of the RFU data structure. This design is comprised of two major processing elements, Restructure Element (RE) and Filter Element (FE), with a central controller.
  4. 4. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Fig. 1 The architecture block diagram for the proposed Deblocking Filter and the re-organization flow for the RFU-based memory structure. Advantages:  low-latency data access  very high processing throughput Software implementation:  Modelsim  Xilinx ISE

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