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Exploiting intracell bit error characteristics to improve min-sum ldpc decoding for mlc nand flash-based storage in mobile device

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Exploiting intracell bit error characteristics to improve min-sum ldpc decoding for mlc nand flash-based storage in mobile device Exploiting intracell bit error characteristics to improve min-sum ldpc decoding for mlc nand flash-based storage in mobile device Exploiting intracell bit error characteristics to improve min-sum ldpc decoding for mlc nand flash-based storage in mobile device

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Exploiting intracell bit error characteristics to improve min-sum ldpc decoding for mlc nand flash-based storage in mobile device

  1. 1. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device Abstract: A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low- density parity-check (LDPC) code and the soft-decision memory sensing become indispensable in the next-generation flash-based solid-state storage devices. However, the use of LDPC codes inevitably increases memory read latency and, hence, degrades speed performance. Motivated by the observation of intracell unbalanced bit error probability and data dependence in the MLC NAND flash memory, this paper proposes two techniques, i.e., intracell data placement interleaving and intracell data dependence aware LDPC decoding, to efficiently improve the LDPC decoding throughput and energy efficiency for the MLC NAND flash-based storage in a mobile device. Experimental results show that, by exploiting the intracell bit-error characteristics, the proposed techniques together can improve the LDPC decoding throughput by up to 84.6% and reduce the energy consumption by up to 33.2% while only incurring less than 0.2% silicon area overhead. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Existing System: Compared with single-level cell, MLC NAND flash memory allows more bits to be stored in a single cell. As the penalty for its high storage density, each MLC NAND flash memory cell has much less margin between two adjacent storage states and is thereby much more prone to errors. In order to reduce its raw bit error probability, Gray code is commonly used when mapping information bits to voltage levels in the MLC cells, so that neighboring levels only differ in 1 bit. Fig. 1 shows an example for 2-bit/cell NAND flash memory. The voltage levels S0, S1, S2, and
  2. 2. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back S3 denote information bits 11, 10, 00, and 01, respectively. The most significant bit (MSB) and the least significant bit (LSB) are associated with upper page and lower page, respectively. As more than 1 bit is stored in a single cell, the program/read operations of MLC NAND flash memory are also complicated. One typical program operation is shown in Fig. 1(a), 2 bit are associated with the four read threshold distribution, and the multilevel programming is achieved in two distinct rounds, one for each bit to be stored. In the first round, the LSB is programmed. If the bit is 1, the voltage threshold of the cell Vthr does not change, and the cell remains in the erased state S0. If the bit is 0, the threshold is increased until it reaches the S2 state. In the second round, the MSB is programmed. The value of voltage threshold depends upon the state of lower page. When the cell remains at the S0 state, the voltage threshold does not change if the bit is 1, while it increases to the S1 state if the bit is 0. When the cell has already been programmed to the S2 state, the voltage threshold increases to the S3 state if the bit is 1, while it moves to the S2 state if the bit is 0.
  3. 3. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Fig. 1. Program and read operations for 2-bit/cell NAND flash memory. (a) Program operation. (b) Read operation.
  4. 4. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Intracell Bit-Error Characteristics Due to the specific data structure and operation inside memory cell, MLC NAND flash memory possesses unique intracell bit-error characteristics that can be exploited for the LDPC decoder design. First, due to the unbalanced voltage threshold arrangement, the bit error probability of the upper page is significantly higher than the lower page, which is referred to as intracell unbalanced bit error probability in this paper. Disadvantages:  decoding iteration is high  error correction strength is low Proposed System: This section describes the proposed techniques and VLSI architecture that exploit intracell bit- error characteristics to improve the throughput and energy efficiency of min-sum LDPC decoding for the MLC NAND flash-based solid-state storage in the mobile devices. The proposed intracell data placement interleaving technique is shown in Fig. 2. To make one codeword contain both the upper page bit and the lower page bit belonging to the same flash memory cell, we divide each codeword into several subblocks, and place the subblocks into upper page and lower page alternately in an interleaved form. In particular, the size of each subblock is chosen to be half of the parallel processing bits of an LDPC decoder, and thus, the decoder could process data that are stored in the same flash cells simultaneously. One potential benefit of the proposed intracell data placement interleaving technique is to reduce the hard- decision decoding failure rate. Due to intracell unbalanced bit error probability, to interleave data placement into both the upper and lower pages can significantly reduce the percentage of data pages that have relatively high BER, even though their average BER almost remains the same.
  5. 5. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Fig. 2. Upper/lower page interleaving diagram in 2-bit/cell NAND flash memory. Intracell Data Dependence Aware Min-Sum Decoding Conventional min-sum LDPC decoding solely relies on the message passing between the variable bits and the check bits. By employing intracell data placement interleaving, we can further benefit from message passing among variable bits, since the error probability of one bit largely depends on the value of the other bit in the same cell. Accordingly, we propose an intracell data dependence aware min-sum LDPC decoding technique that can improve both the error correction strength and the decoding convergence speed. The conventional procedure of min-sum decoding is described as follows, Step 1: Initialize all of the variable-to-check message Mj,i with the LLR of input codeword Ri. Step 2: Calculate the check-to-variable message E j,i for each variable bit with the variable-to- check message. Step 3: Compute the variable-to-check message Mj,i for each parity-check bit with the check-to- variable message and the LLR Ri.
  6. 6. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Step 4: Concurrent with step 3, update the tentative hard decision di for each variable bit, and check whether all the check bits are satisfied. If all the check bits are satisfied, decoding is successful. Otherwise, go to step 2 to start a new decoding iteration until the maximum iteration number is reached. VLSI Architecture Design This section concerns the VLSI architecture design of min-sum LDPC decoding that integrates the above proposed two techniques, i.e., intracell data placement interleaving and intracell data dependence aware min-sum decoding. As shown in Fig. 3, data pages that are read out from flash memory chips are first de-interleaved to recover the code words from two corresponding pages.
  7. 7. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Fig. 3. Overall architecture of the proposed min-sum LDPC decoder that exploits intracell bit- error characteristics. Advantages:
  8. 8. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473 | WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back  reduce the number of decoding iteration  increase the error correction strength Software implementation:  Modelsim  Xilinx ISE

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