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Design and Implementation of High-Speed All-Pass
Transformation-Based Variable Digital Filters by Breaking
the Dependence of Operating Frequency on Filter Order
Abstract:
All-pass transformation (APT)-based variable digital filters (VDFs), also known as frequency
warped VDFs, are typically used in various audio signal-processing applications. In an APT-
based VDF, all-pass filter structures of appropriate order are used to replace the delay elements
in a prototype filter structure. The resultant filter can provide variable frequency responses with
unabridged control over cutoff frequencies on the fly, without updating the filter coefficients. In
this brief, we briefly review the first- and second-order APT-based VDFs along with their
hardware implementation architectures, and provide generalized design procedures to realize
them as per required specifications. We also propose the modified pipelined hardware
implementation architectures for both the first- and second-order APT-based VDFs. Field-
programmable gate array implementation results of different first- and second-order APT-based
VDF designs for both non-pipelined and pipelined implementation architectures are presented.
An analysis of the results shows that the proposed pipelined implementation architectures result
in high-speed VDFs, achieving high operating frequencies that are independent of the prototype
filter order, for both the first- and second-order APT-based VDF designs. The proposed
architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
The APT-based VDFs, also known as frequency warped VDFs, are widely used in applications,
such as audio equalization, the design of warped adaptive filters and discrete Fourier transform-
based filter banks, and hearing aids. Combination of the APT technique with coefficient

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decimation techniques to achieve low complexity implementations of the first- and second-order
APT-based VDFs was recently proposed. In this brief, we present a brief review of the first- and
second-order APT-based VDFs along with their hardware implementation architectures. We
provide generalized design procedures to design these VDFs and propose the modified pipelined
hardware implementation architectures to achieve high-speed filter realizations. The hardware
implementation results obtained for multiple first- and second-order APT-based VDF designs
using the conventional non-pipelined as well as the proposed pipelined implementation
architectures are presented and analyzed. To the best of our knowledge, this is the first work that
addresses the implementation of high-speed APT-based VDFs.
In an APT-based VDF, the all-pass filter structures of appropriate order are used to replace the
delay elements in a prototype filter architecture. The resultant filter can provide variable
frequency responses with unabridged control over cutoff frequency on the fly, without updating
the filter coefficients. Fig. 1(a) shows the generalized implementation architecture of an APT-
based VDF. It is a transposed direct form a finite-impulse response filter architecture in which
every delay element is replaced by P (z), which denotes an all-pass filter structure of appropriate
order. To reduce the implementation complexity of the VDF, only half of the symmetric
prototype filter coefficients are implemented.
First-Order APT-Based VDFs
In the first-order APT-based VDFs, the delay elements in prototype filter architecture are
replaced by the first-order all-pass filter structures [11]. If H (z), A (z), and G (z) are the z-
domain representations of a prototype filter, the first-order all-pass filter, and the first-order
warped version of H(z), respectively, then
G (z) = H (A (z)) (1)
Where A (z) = [(z−1 − α)/ (1 − α.z−1)], |α| < 1 and is real.
Second-Order APT-Based VDFs:

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For the second-order APT-based VDFs, every delay element in prototype filter architecture is
replaced by a second-order all-pass filter structure [10]. If H (z), B (z), and F (z) are the z-
domain representations of a prototype filter, the second-order all-pass filter, and the second-order
warped version of H (z), respectively, then
F (z) = H (B (z)) (2)

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Fig. 1. (a) APT-based VDF: hardware implementation architecture. (b) First-order all-pass filter:
hardware implementation architecture. (c) Second-order all-pass filter: hardware implementation
architecture.
Disadvantages:
 Resource utilization is less
 low operating frequency
Proposed System:
For all the VDF implementations discussed in this design example, the bit-lengths for the
different computational blocks were kept constant. These bit-lengths were selected by verifying
that the resultant frequency responses satisfied the desired passband and stopband peak ripple
specifications. In addition, digital signal processing block inference was disabled since the fixed
filter coefficients and the complex VDF architectures do not gain any significant benefits from
their use. Table II shows the implementation results for the six VDFs obtained after placement
and routing. It was observed that as the prototype filter order increased, the maximum operating
frequencies of the first- and second-order APT-based VDFs decreased proportionately. This was
due to increase in length of the resultant critical data paths.
This dependence of operating frequency of the APT-based VDFs on the prototype filter order
can be a major bottleneck if high operating frequencies are desired along with the stringent
performance specifications, which necessitate the use of higher order prototype filters. To
eliminate the dependence of operating frequency on the prototype filter order, we propose
modified hardware implementation architectures, as shown in Fig. 2(a)–(c). When compared
with the conventional architectures in Fig. 1(a)–(c), the proposed architectures contain additional
delay elements (registers), which enable pipelined implementations and provide constant critical
data paths that are independent of the prototype filter order.

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Fig. 2. (a) APT-based VDF: modified pipelined hardware implementation architecture. (b) First-
order all-pass filter: modified pipelined hardware implementation architecture. (c) Second-order
all-pass filter: modified pipelined hardware implementation architecture.

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Advantages:
 Resource utilization is high
 High operating frequency
Software implementation:
 Modelsim
 Xilinx ISE