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A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling

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A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling

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A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling

A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling

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A 0.521 v fast lock in adpll for supporting dynamic voltage and frequency scaling

  1. 1. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473| WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling Abstract: In energy-efficient processing platforms, such as wearable sensors and implantable medical devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency under various modes of operation. The clock generator used in these platforms should be capable of achieving a faster settling time and has a wider operating voltage range. In this brief, a fast lock- in all-digital phase-locked loop (ADPLL) with two operation modes (0.52/1 V) is presented. The proposed ADPLL can quickly compute the desired digitally controlled oscillator control code with high accuracy. Therefore, the proposed ADPLL can achieve a fast setting time with frequency errors <5% within four clock cycles. The proposed ADPLL is implemented using a standard performance 90-nm CMOS process. The output frequency of the ADPLL ranges from 60 to 600 MHz at 1 V, and from 30 to 120 MHz at 0.52 V. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Enhancement of the project: Existing System: For smart sensing applications, low cost and low power consumption are important. Hence, all- digital PLLs (ADPLLs) are more suitable than analog PLLs, because voltage control schemes face several design challenges in advanced CMOS process at low supply voltages; further, the frequency range for smart sensing applications( < 100MHz) can be easily covered by ADPLLs without necessitating forward body-biased or bulk-driven techniques. In current ADPLL architectures, the binary search algorithm, gear-shifting mechanism, and modified bang–bang algorithm have been proposed for reducing the lock-in time. However, several tens of reference clock cycles are still required to achieve lock-in. A DCO control code
  2. 2. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473| WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back estimating algorithm has been proposed. However, the proposed algorithm requires the DCO resolution. A frequency estimation algorithm that employs the period ratio between the reference clock and the DCO output clock to compute the desired DCO control code for generating the target frequency within two cycles has been proposed. However, the period ratio computed by the frequency counter is an integer number. Therefore, to reduce the frequency error induced by quantization for the period ratio calculation, the multiplication ratio of the ADPLL needs to be maintained at >45. Disadvantages:  power consumption is high Proposed System: Fig. 1 shows the block diagram of the proposed ADPLL. The ADPLL is composed of a phase and frequency detector (PFD), an ADPLL controller, a digital loop filter, a cyclic time-to-digital converter (TDC)-embedded DCO, a frequency finder, and a frequency divider.
  3. 3. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473| WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back Fig. 1. Block diagram of the proposed ADPLL. The proposed cyclic TDC-embedded DCO uses an interpolatorbased fine-tuning stage [18] to maintain a monotonic response between the DCO control code and the output frequency under process, voltage, and temperature (PVT) variations. In addition, the proposed cyclic TDC- embedded DCO can compute the period ratio between the reference clock (REF_CLK) and the DCO output clock (OUT_CLK) as a fixed-point number to reduce the quantization error in the frequency estimation algorithm. CIRCUIT IMPLEMENTATION Fig. 2. Proposed cyclic-TDC-embedded DCO. Fig. 2 shows the circuit diagram of the proposed cyclic TDC-embedded DCO, which is composed of a coarse-tuning stage, a fine-tuning stage, and an embedded cyclic TDC for computing the period ratios (Rmax and Rmin). The coarse-tuning stage of the DCO consists of 64 coarse-tuning delay cells (CDCs), and the coarse-tuning step is the delay time of two NAND gates. The cyclic TDC is composed of 65 pulse-latch DFFs at the output node of the NAND
  4. 4. ONLINE IEEE PROJECTS IeeeXpert.com BUY THIS PROJECT FOR 2000 RS –IeeeXpert.com Mobile: +91-9566492473/+91-9042092473| WhatsApp: 09566492473 Email: contact@ieeexpert.com | Locations: Pondicherry/Chennai Delivering Projects all over India | 100% Output Satisfaction (or) Get Money back gates, a cyclic counter, and a TDC encoder. The TDC resolution is equal to the delay time of two NAND gates or the coarse-tuning resolution of the DCO. The DCO_Decoder decodes the binary 11-bit DCO_code[10:0] into the coarse-tuning and fine-tuning thermometer codes. The TDC_Encoder encodes the 65-bit thermometer code sampled by the pulse-latch DFFs into a 7-bit TDC fractional number (TDC_Frac[6:0]) and the cyclic counter outputs a 9-bit TDC integer number (TDC_Int[8:0]). The fine-tuning stage of the DCO [18] is composed of two parallelly connected tristate buffer arrays operating as an interpolator. By adjusting the number of turned-ON tristate buffers in the arrays, the resolution of the fine-tuning stage can be enhanced to 1/32 that of the coarse-tuning step. The proposed ADPLL uses a cyclic TDC-embedded DCO to compute the fixed-point values of Rmax and Rmin for calculating the target DCO control code (init_code). Advantages:  Reduce the power consumption Software implementation:  Modelsim  Xilinx ISE

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