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Hamming codes provide for FEC using a "block parity" mechanism that can be inexpensively implemented. In general, their use allows the correction of single bit errors and detection of two bit errors per unit data, called a code word.

Hamming code using Verilog hardware description language (HDL).

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- 1. Hamming Encoder and Decoder U. V. Patel College of Engineering Name :- Hetang Chauhan Enrolment - 15014031002 12/16/2016 Hamming Encoder and Decoder 1
- 2. Content • What is Error Correction Code • What is Hamming code • Structure of Hamming Encoder and Decoder • Operation of Hamming Code (7,4,1 ) • Hamming Matrices • Design of the Hamming Encoder and Decoder • Verilog HDL and MATLAB programing • Simulation Results • Conclusion • Future Works • References 12/16/2016 Hamming Encoder and Decoder 2
- 3. What is Error Correction Code • In computer science and information theory, the issue of error correction and detection. • Error correction codes ( ECCs) permit detection and correction of errors that result from noise or other impairments during transmission from the transmitter to the receiver. 12/16/2016 Hamming Encoder and Decoder 3
- 4. What is Hamming code • Hamming code is an error-correction code that can be used to detect single and double-bit errors • It can correct single-bit errors that can occur when binary data is transmitted from one device into another. Single bit error 12/16/2016 Hamming Encoder and Decoder 4
- 5. Structure of Hamming Encoder and Decoder error detecting and correcting codes which deals with the reliable transmission and storage of data 12/16/2016 Hamming Encoder and Decoder 5
- 6. Operation of Hamming Code (7,4,1) Bit 1 2 3 4 5 6 7 Transmitted bit P1 P2 d1 P3 d2 d3 d4 P1 Yes No Yes No Yes No Yes P2 No Yes Yes No No Yes Yes P3 No No No Yes Yes Yes Yes • The goal of Hamming codes is to create a set of parity bits that overlap such that a single-bit error (the bit is logically flipped in value) in a data bit or a parity bit can be detected and corrected. While multiple overlaps can be created, the general method is presented in Hamming codes. 12/16/2016 Hamming Encoder and Decoder 6
- 7. D1 D2 D3 D4 P1 Yes Yes No Yes P2 Yes No Yes Yes P3 No Yes Yes Yes • This table describes which parity bits cover which transmitted bits in the encoded word. For example, P2 covers bits 2, 3, 6, & 7. It also details which transmitted by which parity bit by reading the column. For example, d1 is covered by P1 and P2 but not P3. This table will have a striking resemblance to the parity-check matrix. • Furthermore, if the parity columns in the above table were removed then resemblance to rows 1, 2, & 4 of the code generator matrix (G) below will also be evident. • So, by picking the parity bit coverage correctly, all errors of Hamming distance of 1 can be detected and corrected, which is the point of using a Hamming code. 12/16/2016 Hamming Encoder and Decoder 7
- 8. Hamming Matrices • From this table Hamming codes can be computed in linear algebra terms through matrices because Hamming codes are linear codes. For the purposes of Hamming codes, two Hamming matrices can be defined: the code generator matrix (G) and the parity-check matrix (H) : Hamming Code (n,k)=(7,4) Where , n = code word of length =7 ; k = message bit = 4 ; n-k = parity bit = 7-4 = 3 ; C1 = P1 = d1 ⊕ d2 ⊕ d4 ; C2 = P2 = d1 ⊕ d3 ⊕ d4 ; C3 = d1 ; C4 = P3 = d2 ⊕ d3 ⊕ d4 ; C5 = d2 ; C6 = d3 ; C7 = d4 ; 12/16/2016 Hamming Encoder and Decoder 8
- 9. From this equation we get generator matrix (G) is : 𝐆 = 𝟏 𝟏 𝟏 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟏 𝟎 𝟎 𝟏 And 𝐏 = 𝟏 𝟏 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟏 𝟏 𝟏 ; 𝐏 𝐓 = 𝟏 𝟏 𝟎 𝟏 𝟏 𝟎 𝟏 𝟏 𝟎 𝟏 𝟏 𝟏 ; I = 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟎 𝟏 Cont.. 12/16/2016 Hamming Encoder and Decoder 9
- 10. Cont.. Form the generator matrix to find parity check matrix (H): H = 𝐈 | 𝐏 𝐓 = 𝟏 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟏 𝟏 𝟏 As mentioned above, rows 1, 2, & 3 of should look familiar as they map the data bits to their parity bits: P1 covers d1, d2, d4 P2 covers d1, d3, d4 P3 covers d2, d3, d4 12/16/2016 Hamming Encoder and Decoder 10
- 11. Cont.. Cannel coding Suppose we want to transmit this data over a noisy communication channel. Specifically, a binary symmetric channel meaning that error corruption does not favour either zero or one (it is symmetric in causing errors). Furthermore, all source vectors are assumed to be equal probable. We take the product of d and G, with entries modulo 2, to determine the transmitted Code word (C): Encoding: Now , we will find the Codeword (c): Codeword (C) = d*G Where , d = data ; G = generator matrix 12/16/2016 Hamming Encoder and Decoder 11
- 12. Cont.. let, d = 𝟏 𝟏 𝟎 𝟏 Codeword (C) = 𝟏 𝟏 𝟎 𝟏 * 𝟏 𝟏 𝟏 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟏 𝟎 𝟎 𝟏 = 𝟎 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 This means that 𝟎 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 would be transmitted instead of transmitting 𝟏 𝟏 𝟎 𝟏 . 12/16/2016 Hamming Encoder and Decoder 12
- 13. Decoding : 𝐇 𝐓 = 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟏 𝟏 𝟏 • If no error occurs during transmission, then the received code word r is identical to the transmitted code word (C): • The receiver multiplies r and 𝐇 𝐓 to obtain the syndrome vector , which indicates whether an error has occurred, and if so, for which codeword bit. Performing this multiplication (again, entries modulo 2) : Cont.. 12/16/2016 Hamming Encoder and Decoder 13
- 14. Let r = 𝟏 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 Syndrome (S) = e*𝐇 𝐓 and Syndrome (S) = r*𝐇 𝐓 Where , e = Error pattern r = Received code Error pattern Syndrome (s) = e*𝐇 𝐓 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟏 𝟏 𝟏 Cont.. 12/16/2016 Hamming Encoder and Decoder 14
- 15. Cont.. S = r*𝐇 𝐓 = 𝟏 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 * 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟏 𝟎 𝟏 𝟎 𝟏 𝟏 𝟏 𝟏 𝟏 Modulo 2 addition between r and 𝐡 𝐓 S = 𝟏 ⊕ 𝟎 ⊕ 𝟎 ⊕ 𝟎 ⊕ 𝟏 ⊕ 𝟎 ⊕ 𝟏 𝟎 ⊕ 𝟏 ⊕ 𝟎 ⊕ 𝟎 ⊕ 𝟎 ⊕ 𝟎 ⊕ 𝟏 𝟎 ⊕ 𝟎 ⊕ 12/16/2016 Hamming Encoder and Decoder 15
- 16. From this syndrome matched with error pattern and syndrome table . For 1 0 0 syndrome is error pattern 1 0 0 0 0 0 0 . In this received code (r) the single bit error has occurred in 1st bit of code . The single bit error has occurred. Mathematically, we can Write Correct code word (C) = r – e = 𝟏 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 - 𝟏 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 = 𝟎 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 Correct code word (C) = 𝟎 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 and Data = 𝟏 𝟏 𝟎 𝟏 which is same as the transmitted 4 Bit data. Cont.. 12/16/2016 Hamming Encoder and Decoder 16
- 17. Design of the Hamming Encoder and Decoder 12/16/2016 Hamming Encoder and Decoder 17
- 18. RTL Viewer 12/16/2016 Hamming Encoder and Decoder 18
- 19. Verilog HDL code 12/16/2016 Hamming Encoder and Decoder 19
- 20. Simulation Result 12/16/2016 Hamming Encoder and Decoder 20
- 21. Matlab Code For Encoder 12/16/2016 Hamming Encoder and Decoder 21
- 22. Cont.. 12/16/2016 Hamming Encoder and Decoder 22
- 23. Simulation Results 12/16/2016 Hamming Encoder and Decoder 23
- 24. Cont.. 12/16/2016 Hamming Encoder and Decoder 24
- 25. Verilog code For Decoder 12/16/2016 Hamming Encoder and Decoder 25
- 26. Cont.. 12/16/2016 Hamming Encoder and Decoder 26
- 27. Cont.. 12/16/2016 Hamming Encoder and Decoder 27
- 28. Cont.. 12/16/2016 Hamming Encoder and Decoder 28
- 29. Simulation Results 12/16/2016 Hamming Encoder and Decoder 29
- 30. Cont.. 12/16/2016 Hamming Encoder and Decoder 30
- 31. Cont.. 12/16/2016 Hamming Encoder and Decoder 31
- 32. Matlab code For Decoder 12/16/2016 Hamming Encoder and Decoder 32
- 33. Simulation Results 12/16/2016 Hamming Encoder and Decoder 33
- 34. Conclusion • Error Correction Code (ECC) is a method of error detection and correction in digital data transmission. This project presented design and development of (7, 4, 1) Hamming code using Verilog hardware description language (HDL). • In a communication system that employs forward error-correction coding, the digital information source sends a data sequence to an encoder. The encoder inserts redundant (or parity) bits, thereby outputting a longer sequence of code bits, called a ‘code word.’ These code words can then be transmitted to a receiver, which uses a suitable decoder to extract the original data sequence. • The Verilog code fitted well into small field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs) and application specific integrated circuits (ASICs) and therefore is ideally suited to communication applications that need error-control. 12/16/2016 Hamming Encoder and Decoder 34
- 35. Future work • The Hamming ECC are used in memories and its organization is often more complicated than simply having eight check bits and 64 information bits. Modern server memories may have 16 or 32 information bytes (128 or 256 bits) checked as a single ECC word. Each DRAM chip may store two, three, or four bits in physically adjacent positions. Correspondingly, ECC is done on alphabets of four, eight, or 16 characters— a subject not discussed here. Because the DRAM chips usually come in 8- or 16-bit wide configurations, the memory module often provides more than enough bits for the ECC function. The extra bits might be used for other functions, such as one or two parity bits on the memory address. This allows the memory to check that the address it receives is (probably) the address that the CPU generated. 12/16/2016 Hamming Encoder and Decoder 35
- 36. References [1] Data communication and networking, Behrouz A. Forouzan, 4th edition, Tata McGrawHill publication. [2] http://hamming (7,4) code Discussion and implementation. [3] Hardware implementation of a single bit error code correction by constantion IANA, Gheorghe SERBAN, Ion TUTANESCU, Petre ANGHE--LESCU. [4] Information Theory Coding and Cryptography by Ranjan Bose. [5] Verilog HDL:A guide to digital design and synthesis,second edition by Sameer Palnitkar. [6] Hamming W.Richard. Coding and information and theory, Prentice-Hall chapter 3. 12/16/2016 Hamming Encoder and Decoder 36
- 37. Thank You... 12/16/2016 Hamming Encoder and Decoder 37

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