Intel Architecture                   Software Developer’s                                Manual                           ...
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppelor ...
TABLE OF CONTENTSCHAPTER 1ABOUT THIS MANUAL1.1.   OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL,       VO...
TABLE OF CONTENTS3.2.      INSTRUCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
TABLE OF CONTENTSDAA—Decimal Adjust AL after Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
TABLE OF CONTENTS     FSTENV/FNSTENV—Store FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-251 ...
TABLE OF CONTENTSMAXPS—Packed Single-FP Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .       ...
TABLE OF CONTENTS       PMINSW—Packed Signed Integer Word Minimum . . . . . . . . . . . . . . . . . . . . . . . . . .3-514...
TABLE OF CONTENTS        SHUFPS—Shuffle Single-FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
TABLE OF CONTENTSA.2.6.5.            Escape Opcodes with DA as First Byte                   ............................  ...
TABLE OF FIGURESFigure 1-1.    Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
TABLE OF FIGURESFigure 3-48.   Operation of the MOVSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
TABLE OF FIGURESFigure 3-98.    Operation of the UCOMISS Instruction, Condition Four . . . . . . . . . . . . . . . 3-692Fi...
TABLE OF FIGURESxiv
TABLE OF TABLESTable 2-1.    16-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . .2-5...
TABLE OF TABLESTable B-15.   Streaming SIMD Extensions Instruction Behavior with Prefixes . . . . . . . . . B-25Table B-16...
1About This Manual
CHAPTER 1                                                     ABOUT THIS MANUALThe Intel Architecture Software Developer’s...
ABOUT THIS MANUALare arranged in alphabetical order. The FPU, MMX™ Technology instructions, and StreamingSIMD Extensions a...
ABOUT THIS MANUALChapter 10 — Input/Output. Describes the processor’s I/O architecture, including I/O portaddressing, the ...
ABOUT THIS MANUALChapter 4 — Protection. Describes the support for page and segment protection provided inthe Intel Archit...
ABOUT THIS MANUALChapter 16 — 8086 Emulation. Describes the real-address and virtual-8086 modes of the IntelArchitecture.C...
ABOUT THIS MANUAL                                         Data Structure                  Highest           24 23    16 15...
ABOUT THIS MANUAL1.4.3.      Instruction OperandsWhen instructions are represented symbolically, a subset of the Intel Arc...
ABOUT THIS MANUALThe processor also supports segmented addressing. This is a form of addressing where aprogram may have ma...
ABOUT THIS MANUAL1.5.     RELATED LITERATUREThe following books contain additional material related to Intel processors:• ...
ABOUT THIS MANUAL1-10
2Instruction Format
CHAPTER 2                                                            INSTRUCTION FORMATThis chapter describes the instruct...
INSTRUCTION FORMAT•     Segment override.      — 2EH—CS segment override prefix.      — 36H—SS segment override prefix.   ...
INSTRUCTION FORMATCertain encodings of the ModR/M byte require a second addressing byte, the SIB byte, to fullyspecify the...
INSTRUCTION FORMATsented by the sixth row, labeled “/digit (Opcode)”. The five rows above give the byte, word, anddoublewo...
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24319102

  1. 1. Intel Architecture Software Developer’s Manual Volume 2: Instruction Set Reference NOTE: The Intel Architecture Software Developer’s Manual consists ofthree volumes: Basic Architecture, Order Number 243190; Instruction Set Reference, Order Number 243191; and the System Programming Guide, Order Number 243192. Please refer to all three volumes when evaluating your design needs. 1999
  2. 2. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppelor otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms andConditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or impliedwarranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particularpurpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products arenot intended for use in medical, life saving, or life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or“undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts orincompatibilities arising from future changes to them.Intel’s Intel Architecture processors (e.g., Pentium®, Pentium® II, Pentium® III, and Pentium® Pro processors) maycontain design defects or errors known as errata which may cause the product to deviate from publishedspecifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing yourproduct order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature,may be obtained by calling 1-800-548-4725, or by visiting Intels literature center at http://www.intel.com.COPYRIGHT © INTEL CORPORATION 1999*THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS.
  3. 3. TABLE OF CONTENTSCHAPTER 1ABOUT THIS MANUAL1.1. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCE 1-11.2. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE 1-21.3. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE 1-31.4. NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.4.1. Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-51.4.2. Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-61.4.3. Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.4.4. Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.4.5. Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.4.6. Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-81.5. RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9CHAPTER 2INSTRUCTION FORMAT2.1. GENERAL INSTRUCTION FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2. INSTRUCTION PREFIXES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.3. OPCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22.4. MODR/M AND SIB BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22.5. DISPLACEMENT AND IMMEDIATE BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.6. ADDRESSING-MODE ENCODING OF MODR/M AND SIB BYTES . . . . . . . . . . . . 2-3CHAPTER 3INSTRUCTION SET REFERENCE3.1. INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . 3-13.1.1. Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13.1.1.1. Opcode Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23.1.1.2. Instruction Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33.1.1.3. Description Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53.1.1.4. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53.1.2. Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63.1.3. Intel C/C++ Compiler Intrinsics Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-93.1.3.1. The Intrinsics API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-93.1.3.2. MMX™ Technology Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-103.1.3.3. SIMD Floating-Point Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-103.1.4. Flags Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-113.1.5. FPU Flags Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-123.1.6. Protected Mode Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-123.1.7. Real-Address Mode Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-123.1.8. Virtual-8086 Mode Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-133.1.9. Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-143.1.10. SIMD Floating-Point Exceptions - Streaming SIMD Extensions Only . . . . . . . . .3-14 iii
  4. 4. TABLE OF CONTENTS3.2. INSTRUCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 AAA—ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 AAD—ASCII Adjust AX Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20 ADC—Add with Carry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21 ADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23 ADDPS—Packed Single-FP Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25 ADDSS—Scalar Single-FP Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27 AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-30 ANDNPS—Bit-wise Logical And Not For Single-FP. . . . . . . . . . . . . . . . . . . . . . . . . . .3-32 ANDPS—Bit-wise Logical And For Single FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34 ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-36 BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-38 BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-40 BSR—Bit Scan Reverse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42 BSWAP—Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44 BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45 BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-47 BTR—Bit Test and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49 BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51 CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53 CBW/CWDE—Convert Byte to Word/Convert Word to Doubleword . . . . . . . . . . . . . .3-64 CDQ—Convert Double to Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-65 CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-66 CLD—Clear Direction Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-67 CLI—Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-68 CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70 CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71 CMOVcc—Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72 CMP—Compare Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-76 CMPPS—Packed Single-FP Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-78 CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands. . . . . . . . . . . . . . . . . .3-87 CMPSS—Scalar Single-FP Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-90 CMPXCHG—Compare and Exchange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-100 CMPXCHG8B—Compare and Exchange 8 Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . .3-102 COMISS—Scalar Ordered Single-FP Compare and Set EFLAGS . . . . . . . . . . . . . .3-104 CPUID—CPU Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-111 CVTPI2PS—Packed Signed INT32 to Packed Single-FP Conversion . . . . . . . . . . .3-119 CVTPS2PI—Packed Single-FP to Packed INT32 Conversion. . . . . . . . . . . . . . . . . .3-123 CVTSI2SS—Scalar Signed INT32 to Single-FP Conversion . . . . . . . . . . . . . . . . . . .3-127 CVTSS2SI—Scalar Single-FP to Signed INT32 Conversion . . . . . . . . . . . . . . . . . . .3-130 CVTTPS2PI—Packed Single-FP to Packed INT32 Conversion (Truncate). . . . . . . .3-133 CVTTSS2SI—Scalar Single-FP to Signed INT32 Conversion (Truncate) . . . . . . . . .3-137 CWD/CDQ—Convert Word to Doubleword/Convert Doubleword to Quadword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-141 CWDE—Convert Word to Doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-142iv
  5. 5. TABLE OF CONTENTSDAA—Decimal Adjust AL after Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143DAS—Decimal Adjust AL after Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145DEC—Decrement by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-146DIV—Unsigned Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148DIVPS—Packed Single-FP Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-151DIVSS—Scalar Single-FP Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154EMMS—Empty MMX™ State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156ENTER—Make Stack Frame for Procedure Parameters . . . . . . . . . . . . . . . . . . . . . 3-158F2XM1—Compute 2x–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161FABS—Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163FADD/FADDP/FIADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-165FBLD—Load Binary Coded Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-169FBSTP—Store BCD Integer and Pop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-171FCHS—Change Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174FCLEX/FNCLEX—Clear Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-176FCMOVcc—Floating-Point Conditional Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178FCOM/FCOMP/FCOMPP—Compare Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-180FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Real and Set EFLAGS . . . . . . . 3-183FCOS—Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-186FDECSTP—Decrement Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-188FDIV/FDIVP/FIDIV—Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-189FDIVR/FDIVRP/FIDIVR—Reverse Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-193FFREE—Free Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-197FICOM/FICOMP—Compare Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-198FILD—Load Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-200FINCSTP—Increment Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-202FINIT/FNINIT—Initialize Floating-Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-203FIST/FISTP—Store Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-205FLD—Load Real. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-208FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . 3-210FLDCW—Load Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-212FLDENV—Load FPU Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-214FMUL/FMULP/FIMUL—Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-216FNOP—No Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-220FPATAN—Partial Arctangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-221FPREM—Partial Remainder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-223FPREM1—Partial Remainder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-226FPTAN—Partial Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-229FRNDINT—Round to Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-231FRSTOR—Restore FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-232FSAVE/FNSAVE—Store FPU State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-235FSCALE—Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-238FSIN—Sine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-240FSINCOS—Sine and Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-242FSQRT—Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-244FST/FSTP—Store Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-246FSTCW/FNSTCW—Store Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-249 v
  6. 6. TABLE OF CONTENTS FSTENV/FNSTENV—Store FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-251 FSTSW/FNSTSW—Store Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-254 FSUB/FSUBP/FISUB—Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-257 FSUBR/FSUBRP/FISUBR—Reverse Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-261 FTST—TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-265 FUCOM/FUCOMP/FUCOMPP—Unordered Compare Real . . . . . . . . . . . . . . . . . . .3-267 FWAIT—Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-270 FXAM—Examine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-271 FXCH—Exchange Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-273 FXRSTOR—Restore FP and MMX™ State and Streaming SIMD Extension State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-275 FXSAVE—Store FP and MMX™ State and Streaming SIMD Extension State . . . . .3-279 FXTRACT—Extract Exponent and Significand . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-285 FYL2X—Compute y * log2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-287 FYL2XP1—Compute y * log2(x +1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-289 HLT—Halt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-291 IDIV—Signed Divide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-292 IMUL—Signed Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-295 IN—Input from Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-299 INC—Increment by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-301 INS/INSB/INSW/INSD—Input from Port to String . . . . . . . . . . . . . . . . . . . . . . . . . . .3-303 INT n/INTO/INT 3—Call to Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-306 INVD—Invalidate Internal Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-318 INVLPG—Invalidate TLB Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-320 IRET/IRETD—Interrupt Return. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-321 Jcc—Jump if Condition Is Met . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-329 JMP—Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-333 LAHF—Load Status Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-341 LAR—Load Access Rights Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-342 LDMXCSR—Load Streaming SIMD Extension Control/Status . . . . . . . . . . . . . . . . .3-345 LDS/LES/LFS/LGS/LSS—Load Far Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-349 LEA—Load Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-353 LEAVE—High Level Procedure Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-355 LES—Load Full Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-357 LFS—Load Full Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-358 LGDT/LIDT—Load Global/Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . .3-359 LGS—Load Full Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-361 LLDT—Load Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-362 LIDT—Load Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-364 LMSW—Load Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-365 LOCK—Assert LOCK# Signal Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-367 LODS/LODSB/LODSW/LODSD—Load String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-369 LOOP/LOOPcc—Loop According to ECX Counter . . . . . . . . . . . . . . . . . . . . . . . . . .3-372 LSL—Load Segment Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-375 LSS—Load Full Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-379 LTR—Load Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-380 MASKMOVQ—Byte Mask Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-382vi
  7. 7. TABLE OF CONTENTSMAXPS—Packed Single-FP Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-386MAXSS—Scalar Single-FP Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-390MINPS—Packed Single-FP Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-394MINSS—Scalar Single-FP Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-398MOV—Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-402MOV—Move to/from Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-407MOV—Move to/from Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-409MOVAPS—Move Aligned Four Packed Single-FP. . . . . . . . . . . . . . . . . . . . . . . . . . 3-411MOVD—Move 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-414MOVHLPS— High to Low Packed Single-FP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-417MOVHPS—Move High Packed Single-FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-419MOVLHPS—Move Low to High Packed Single-FP . . . . . . . . . . . . . . . . . . . . . . . . . 3-422MOVLPS—Move Low Packed Single-FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-424MOVMSKPS—Move Mask To Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-427MOVNTPS—Move Aligned Four Packed Single-FP Non Temporal. . . . . . . . . . . . . 3-429MOVNTQ—Move 64 Bits Non Temporal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431MOVQ—Move 64 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-433MOVS/MOVSB/MOVSW/MOVSD—Move Data from String to String . . . . . . . . . . . 3-435MOVSS—Move Scalar Single-FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-438MOVSX—Move with Sign-Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-441MOVUPS—Move Unaligned Four Packed Single-FP . . . . . . . . . . . . . . . . . . . . . . . 3-443MOVZX—Move with Zero-Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-446MUL—Unsigned Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-448MULPS—Packed Single-FP Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-450MULSS—Scalar Single-FP Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-452NEG—Twos Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-454NOP—No Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-456NOT—Ones Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-457OR—Logical Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-459ORPS—Bit-wise Logical OR for Single-FP Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-461OUT—Output to Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-463OUTS/OUTSB/OUTSW/OUTSD—Output String to Port . . . . . . . . . . . . . . . . . . . . . 3-465PACKSSWB/PACKSSDW—Pack with Signed Saturation . . . . . . . . . . . . . . . . . . . . 3-469PACKUSWB—Pack with Unsigned Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-472PADDB/PADDW/PADDD—Packed Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-475PADDSB/PADDSW—Packed Add with Saturation . . . . . . . . . . . . . . . . . . . . . . . . . 3-479PADDUSB/PADDUSW—Packed Add Unsigned with Saturation . . . . . . . . . . . . . . . 3-482PAND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-485PANDN—Logical AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-487PAVGB/PAVGW—Packed Average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-489PCMPEQB/PCMPEQW/PCMPEQD—Packed Compare for Equal . . . . . . . . . . . . . 3-493PCMPGTB/PCMPGTW/PCMPGTD—Packed Compare for Greater Than . . . . . . . 3-497PEXTRW—Extract Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-501PINSRW—Insert Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-503PMADDWD—Packed Multiply and Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-505PMAXSW—Packed Signed Integer Word Maximum . . . . . . . . . . . . . . . . . . . . . . . . 3-508PMAXUB—Packed Unsigned Integer Byte Maximum . . . . . . . . . . . . . . . . . . . . . . . 3-511 vii
  8. 8. TABLE OF CONTENTS PMINSW—Packed Signed Integer Word Minimum . . . . . . . . . . . . . . . . . . . . . . . . . .3-514 PMINUB—Packed Unsigned Integer Byte Minimum . . . . . . . . . . . . . . . . . . . . . . . . .3-517 PMOVMSKB—Move Byte Mask To Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-520 PMULHUW—Packed Multiply High Unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-522 PMULHW—Packed Multiply High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-525 PMULLW—Packed Multiply Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-528 POP—Pop a Value from the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-531 POPA/POPAD—Pop All General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . .3-536 POPF/POPFD—Pop Stack into EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-538 POR—Bitwise Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-541 PREFETCH—Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-543 PSADBW—Packed Sum of Absolute Differences . . . . . . . . . . . . . . . . . . . . . . . . . . .3-545 PSHUFW—Packed Shuffle Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-548 PSLLW/PSLLD/PSLLQ—Packed Shift Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . .3-550 PSRAW/PSRAD—Packed Shift Right Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-555 PSRLW/PSRLD/PSRLQ—Packed Shift Right Logical. . . . . . . . . . . . . . . . . . . . . . . .3-558 PSUBB/PSUBW/PSUBD—Packed Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-563 PSUBSB/PSUBSW—Packed Subtract with Saturation . . . . . . . . . . . . . . . . . . . . . . .3-567 PSUBUSB/PSUBUSW—Packed Subtract Unsigned with Saturation . . . . . . . . . . . .3-570 PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ—Unpack High Packed Data . . . . . . .3-573 PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ—Unpack Low Packed Data . . . . . . . .3-577 PUSH—Push Word or Doubleword Onto the Stack. . . . . . . . . . . . . . . . . . . . . . . . . .3-581 PUSHA/PUSHAD—Push All General-Purpose Registers . . . . . . . . . . . . . . . . . . . . .3-584 PUSHF/PUSHFD—Push EFLAGS Register onto the Stack . . . . . . . . . . . . . . . . . . .3-587 PXOR—Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-589 RCL/RCR/ROL/ROR-—Rotate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-591 RCPPS—Packed Single-FP Reciprocal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-596 RCPSS—Scalar Single-FP Reciprocal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-598 RDMSR—Read from Model Specific Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-600 RDPMC—Read Performance-Monitoring Counters. . . . . . . . . . . . . . . . . . . . . . . . . .3-602 RDTSC—Read Time-Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-604 REP/REPE/REPZ/REPNE /REPNZ—Repeat String Operation Prefix . . . . . . . . . . .3-605 RET—Return from Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-608 ROL/ROR—Rotate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-615 RSM—Resume from System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .3-616 RSQRTPS—Packed Single-FP Square Root Reciprocal . . . . . . . . . . . . . . . . . . . . .3-617 RSQRTSS—Scalar Single-FP Square Root Reciprocal . . . . . . . . . . . . . . . . . . . . . .3-619 SAHF—Store AH into Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-621 SAL/SAR/SHL/SHR—Shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-622 SBB—Integer Subtraction with Borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-627 SCAS/SCASB/SCASW/SCASD—Scan String . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-629 SETcc—Set Byte on Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-632 SFENCE—Store Fence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-634 SGDT/SIDT—Store Global/Interrupt Descriptor Table Register . . . . . . . . . . . . . . . .3-636 SHL/SHR—Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-639 SHLD—Double Precision Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-640 SHRD—Double Precision Shift Right. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-643viii
  9. 9. TABLE OF CONTENTS SHUFPS—Shuffle Single-FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-646 SIDT—Store Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-651 SLDT—Store Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-652 SMSW—Store Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-654 SQRTPS—Packed Single-FP Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-656 SQRTSS—Scalar Single-FP Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-659 STC—Set Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-662 STD—Set Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-663 STI—Set Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-664 STMXCSR—Store Streaming SIMD Extension Control/Status . . . . . . . . . . . . . . . . 3-666 STOS/STOSB/STOSW/STOSD—Store String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-668 STR—Store Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-671 SUB—Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-673 SUBPS—Packed Single-FP Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-675 SUBSS—Scalar Single-FP Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-678 SYSENTER—Fast Transition to System Call Entry Point . . . . . . . . . . . . . . . . . . . . 3-681 SYSEXIT—Fast Transition from System Call Entry Point . . . . . . . . . . . . . . . . . . . . 3-685 TEST—Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-688 UCOMISS—Unordered Scalar Single-FP compare and set EFLAGS . . . . . . . . . . . 3-690 UD2—Undefined Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-697 UNPCKHPS—Unpack High Packed Single-FP Data . . . . . . . . . . . . . . . . . . . . . . . . 3-698 UNPCKLPS—Unpack Low Packed Single-FP Data . . . . . . . . . . . . . . . . . . . . . . . . 3-701 VERR/VERW—Verify a Segment for Reading or Writing. . . . . . . . . . . . . . . . . . . . . 3-704 WAIT/FWAIT—Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-707 WBINVD—Write Back and Invalidate Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-708 WRMSR—Write to Model Specific Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-710 XADD—Exchange and Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-712 XCHG—Exchange Register/Memory with Register . . . . . . . . . . . . . . . . . . . . . . . . . 3-714 XLAT/XLATB—Table Look-up Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-716 XOR—Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-718 XORPS—Bit-wise Logical Xor for Single-FP Data . . . . . . . . . . . . . . . . . . . . . . . . . . 3-720APPENDIX AOPCODE MAPA.1. KEY TO ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1A.1.1. Codes for Addressing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1A.1.2. Codes for Operand Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3A.1.3. Register Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3A.2. OPCODE LOOK-UP EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3A.2.1. One-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4A.2.2. Two-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4A.2.3. Opcode Map Shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5A.2.4. Opcode Map Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5A.2.5. Opcode Extensions For One- And Two-byte Opcodes . . . . . . . . . . . . . . . . . . . A-10A.2.6. Escape Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12A.2.6.1. Opcodes with ModR/M Bytes in the 00H through BFH Range . . . . . . . . . . . A-12A.2.6.2. Opcodes with ModR/M Bytes outside the 00H through BFH Range. . . . . . . A-12A.2.6.3. Escape Opcodes with D8 as First Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12A.2.6.4. Escape Opcodes with D9 as First Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14 ix
  10. 10. TABLE OF CONTENTSA.2.6.5. Escape Opcodes with DA as First Byte ............................ A-15A.2.6.6. Escape Opcodes with DB as First Byte ............................ A-16A.2.6.7. Escape Opcodes with DC as First Byte ............................ A-18A.2.6.8. Escape Opcodes with DD as First Byte ............................ A-19A.2.6.9. Escape Opcodes with DE as First Byte ............................ A-21A.2.6.10. Escape Opcodes with DF As First Byte ............................ A-22APPENDIX BINSTRUCTION FORMATS AND ENCODINGSB.1. MACHINE INSTRUCTION FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1B.1.1. Reg Field (reg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2B.1.2. Encoding of Operand Size Bit (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.1.3. Sign Extend (s) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.1.4. Segment Register Field (sreg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4B.1.5. Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4B.1.6. Condition Test Field (tttn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5B.1.7. Direction (d) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5B.2. INTEGER INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . B-6B.3. MMX™ INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . B-19B.3.1. Granularity Field (gg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19B.3.2. MMX™ and General-Purpose Register Fields (mmxreg and reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19B.3.3. MMX™ Instruction Formats and Encodings Table . . . . . . . . . . . . . . . . . . . . . . B-20B.4. STREAMING SIMD EXTENSION FORMATS AND ENCODINGS TABLE . . . . . . B-24B.4.1. Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24B.4.2. Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-26B.4.3. Formats and Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27B.5. FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . B-36APPENDIX CCOMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTSC.1. SIMPLE INTRINSICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2C.2. COMPOSITE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11x
  11. 11. TABLE OF FIGURESFigure 1-1. Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Figure 2-1. Intel Architecture Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1Figure 3-1. Bit Offset for BIT[EAX,21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8Figure 3-2. Memory Bit Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12Figure 3-3. Operation of the ADDPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25Figure 3-4. Operation of the ADDSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27Figure 3-5. Operation of the ANDNPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32Figure 3-6. Operation of the ANDPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34Figure 3-7. Operation of the CMPPS (Imm8=0) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-78Figure 3-8. Operation of the CMPPS (Imm8=1) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-78Figure 3-9. Operation of the CMPPS (Imm8=2) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-79Figure 3-10. Operation of the CMPPS (Imm8=3) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-79Figure 3-11. Operation of the CMPPS (Imm8=4) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-80Figure 3-12. Operation of the CMPPS (Imm8=5) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-80Figure 3-13. Operation of the CMPPS (Imm8=6) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-81Figure 3-14. Operation of the CMPPS (Imm8=7) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-81Figure 3-15. Operation of the CMPSS (Imm8=0) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-92Figure 3-16. Operation of the CMPSS (Imm8=1) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-92Figure 3-17. Operation of the CMPSS (Imm8=2) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-93Figure 3-18. Operation of the CMPSS (Imm8=3) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-93Figure 3-19. Operation of the CMPSS (Imm8=4) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-94Figure 3-20. Operation of the CMPSS (Imm8=5) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-94Figure 3-21. Operation of the CMPSS (Imm8=6) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-95Figure 3-22. Operation of the CMPSS (Imm8=7) Instruction . . . . . . . . . . . . . . . . . . . . . . .3-95Figure 3-23. Operation of the COMISS Instruction, Condition One . . . . . . . . . . . . . . . . .3-104Figure 3-24. Operation of the COMISS Instruction, Condition Two . . . . . . . . . . . . . . . . .3-105Figure 3-25. Operation of the COMISS Instruction, Condition Three . . . . . . . . . . . . . . . .3-105Figure 3-26. Operation of the COMISS Instruction, Condition Four . . . . . . . . . . . . . . . . .3-106Figure 3-27. Version and Feature Information in Registers EAX and EDX. . . . . . . . . . . .3-112Figure 3-28. Operation of the CVTPI2PS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-119Figure 3-29. Operation of the CVTPS2PI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-123Figure 3-30. Operation of the CVTSI2SS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-127Figure 3-31. Operation of the CVTSS2SI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-130Figure 3-32. Operation of the CVTTPS2PI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . .3-133Figure 3-33. Operation of the CVTTSS2SI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . .3-137Figure 3-34. Operation of the DIVPS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-151Figure 3-35. Operation of the DIVSS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-154Figure 3-36. Operation of the MAXPS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-386Figure 3-37. Operation of the MAXSS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-390Figure 3-38. Operation of the MINPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-394Figure 3-39. Operation of the MINSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-398Figure 3-40. Operation of the MOVAPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-411Figure 3-41. Operation of the MOVD Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-414Figure 3-42. Operation of the MOVHLPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-417Figure 3-43. Operation of the MOVHPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-419Figure 3-44. Operation of the MOVLHPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-422Figure 3-45. Operation of the MOVLPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-424Figure 3-46. Operation of the MOVMSKPS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . .3-427Figure 3-47. Operation of the MOVQ Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-433 xi
  12. 12. TABLE OF FIGURESFigure 3-48. Operation of the MOVSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-438Figure 3-49. Operation of the MOVUPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-443Figure 3-50. Operation of the MULPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-450Figure 3-51. Operation of the MULSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-452Figure 3-52. Operation of the ORPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-461Figure 3-53. Operation of the PACKSSDW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . .3-469Figure 3-54. Operation of the PACKUSWB Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . .3-472Figure 3-55. Operation of the PADDW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-475Figure 3-56. Operation of the PADDSW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-479Figure 3-57. Operation of the PADDUSB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-482Figure 3-58. Operation of the PAND Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-485Figure 3-59. Operation of the PANDN Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-487Figure 3-60. Operation of the PAVGB/PAVGW Instruction. . . . . . . . . . . . . . . . . . . . . . . .3-489Figure 3-61. Operation of the PCMPEQW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . .3-493Figure 3-62. Operation of the PCMPGTW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-497Figure 3-63. Operation of the PEXTRW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-501Figure 3-64. Operation of the PINSRW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-503Figure 3-65. Operation of the PMADDWD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . .3-505Figure 3-66. Operation of the PMAXSW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-508Figure 3-67. Operation of the PMAXUB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-511Figure 3-68. Operation of the PMINSW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-514Figure 3-69. Operation of the PMINUB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-517Figure 3-70. Operation of the PMOVMSKB Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . .3-520Figure 3-71. Operation of the PMULHUW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-522Figure 3-72. Operation of the PMULHW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-525Figure 3-73. Operation of the PMULLW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-528Figure 3-74. Operation of the POR Instruction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-541Figure 3-75. Operation of the PSADBW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-545Figure 3-76. Operation of the PSHUFW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-548Figure 3-77. Operation of the PSLLW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-550Figure 3-78. Operation of the PSRAW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-555Figure 3-79. Operation of the PSRLW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-558Figure 3-80. Operation of the PSUBW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-563Figure 3-81. Operation of the PSUBSW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-567Figure 3-82. Operation of the PSUBUSB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-570Figure 3-83. High-Order Unpacking and Interleaving of Bytes With the PUNPCKHBW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-573Figure 3-84. Low-Order Unpacking and Interleaving of Bytes With the PUNPCKLBW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-577Figure 3-85. Operation of the PXOR Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-589Figure 3-86. Operation of the RCPPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-596Figure 3-87. Operation of the RCPSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-598Figure 3-88. Operation of the RSQRTPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-617Figure 3-89. Operation of the RSQRTSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-619Figure 3-90. Operation of the SHUFPS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-647Figure 3-91. Operation of the SQRTPS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-656Figure 3-92. Operation of the SQRTSS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-659Figure 3-93. Operation of the SUBPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-675Figure 3-94. Operation of the SUBSS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-678Figure 3-95. Operation of the UCOMISS Instruction, Condition One . . . . . . . . . . . . . . . .3-690Figure 3-96. Operation of the UCOMISS Instruction, Condition Two . . . . . . . . . . . . . . . .3-691Figure 3-97. Operation of the UCOMISS Instruction, Condition Three . . . . . . . . . . . . . . .3-691xii
  13. 13. TABLE OF FIGURESFigure 3-98. Operation of the UCOMISS Instruction, Condition Four . . . . . . . . . . . . . . . 3-692Figure 3-99. Operation of the UNPCKHPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 3-699Figure 3-100. Operation of the UNPCKLPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 3-702Figure 3-101. Operation of the XORPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-720Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10Figure B-1. General Machine Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1Figure B-2. Key to Codes for MMX™ Data Type Cross-Reference. . . . . . . . . . . . . . . . . B-20Figure B-3. Key to Codes for Streaming SIMD Extensions Data Type Cross-Reference B-27 xiii
  14. 14. TABLE OF FIGURESxiv
  15. 15. TABLE OF TABLESTable 2-1. 16-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . .2-5Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . .2-6Table 2-3. 32-Bit Addressing Forms with the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7Table 3-1. Register Encodings Associated with the +rb, +rw, and +rd Nomenclature. . . .3-3Table 3-2. Exception Mnemonics, Names, and Vector Numbers . . . . . . . . . . . . . . . . . .3-13Table 3-3. Floating-Point Exception Mnemonics and Names . . . . . . . . . . . . . . . . . . . . .3-14Table 3-4. SIMD Floating-Point Exception Mnemonics and Names . . . . . . . . . . . . . . . .3-15Table 3-5. Streaming SIMD Extensions Faults (Interrupts 6 & 7) . . . . . . . . . . . . . . . . . .3-16Table 3-6. Information Returned by CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . . . .3-111Table 3-7. Processor Type Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-113Table 3-8. Feature Flags Returned in EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-114Table 3-9. Encoding of Cache and TLB Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . .3-116Table A-1. Notes on Instruction Set Encoding Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5Table A-2. One-byte Opcode Map (Left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6Table A-3. One-byte Opcode Map (Right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7Table A-4. Two-byte Opcode Map (Left) (First Byte is OFH) . . . . . . . . . . . . . . . . . . . . . . A-8Table A-5. Two-byte Opcode Map (Right) (First Byte is OFH). . . . . . . . . . . . . . . . . . . . . A-9Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group Number. . . A-11Table A-7. D8 Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-12Table A-8. D8 Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-13Table A-9. D9 Opcode Map When ModR/M Byte is Within 00H to BFH1. . . . . . . . . . . . A-14Table A-10. D9 Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-15Table A-11. DA Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-15Table A-12. DA Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-16Table A-13. DB Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-17Table A-14. DB Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-17Table A-15. DC Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-18Table A-16. DC Opcode Map When ModR/M Byte is Outside 00H to BFH4 . . . . . . . . . . A-19Table A-17. DD Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-20Table A-18. DD Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-20Table A-19. DE Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-21Table A-20. DE Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-22Table A-21. DF Opcode Map When ModR/M Byte is Within 00H to BFH1 . . . . . . . . . . . A-23Table A-22. DF Opcode Map When ModR/M Byte is Outside 00H to BFH1 . . . . . . . . . . A-23Table B-1. Special Fields Within Instruction Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . B-2Table B-2. Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . B-2Table B-3. Encoding of reg Field When w Field is Present in Instruction. . . . . . . . . . . . . B-3Table B-4. Encoding of Operand Size (w) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Table B-5. Encoding of Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Table B-6. Encoding of the Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . B-4Table B-7. Encoding of Special-Purpose Register (eee) Field. . . . . . . . . . . . . . . . . . . . . B-4Table B-8. Encoding of Conditional Test (tttn) Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5Table B-9. Encoding of Operation Direction (d) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6Table B-10. Integer Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . B-6Table B-11. Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . B-19Table B-12. Encoding of the MMX™ Register Field (mmxreg) . . . . . . . . . . . . . . . . . . . . B-19Table B-13. Encoding of the General-Purpose Register Field (reg) When Used in MMX™ Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-20Table B-14. MMX™ Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . B-21xv
  16. 16. TABLE OF TABLESTable B-15. Streaming SIMD Extensions Instruction Behavior with Prefixes . . . . . . . . . B-25Table B-16. SIMD Integer Instructions - Behavior with Prefixes . . . . . . . . . . . . . . . . . . . B-25Table B-17. Cacheability Control Instruction Behavior with Prefixes . . . . . . . . . . . . . . . B-25Table B-18. Key to Streaming SIMD Extensions Naming Convention . . . . . . . . . . . . . . . B-26Table B-19. Encoding of the SIMD Floating-Point Register Field . . . . . . . . . . . . . . . . . . B-27Table B-20. Encoding of the SIMD-Integer Register Field . . . . . . . . . . . . . . . . . . . . . . . . B-34Table B-21. Encoding of the Streaming SIMD Extensions Cacheability Control Register Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-35Table B-22. General Floating-Point Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . B-36Table B-23. Floating-Point Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . B-37Table C-1. Simple Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2Table C-2. Composite Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11xvi
  17. 17. 1About This Manual
  18. 18. CHAPTER 1 ABOUT THIS MANUALThe Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference(Order Number 243191) is part of a three-volume set that describes the architecture andprogramming environment of all Intel Architecture processors. The other two volumes in thisset are:• The Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 243190).• The Intel Architecture Software Developer’s Manual, Volume 3: System Programing Guide (Order Number 243192).The Intel Architecture Software Developer’s Manual, Volume 1, describes the basic architectureand programming environment of an Intel Architecture processor; the Intel Architecture Soft-ware Developer’s Manual, Volume 2, describes the instructions set of the processor and theopcode structure. These two volumes are aimed at application programmers who are writingprograms to run under existing operating systems or executives. The Intel Architecture SoftwareDeveloper’s Manual, Volume 3, describes the operating-system support environment of an IntelArchitecture processor, including memory management, protection, task management, interruptand exception handling, and system management mode. It also provides Intel Architectureprocessor compatibility information. This volume is aimed at operating-system and BIOSdesigners and programmers.1.1. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCEThe contents of this manual are as follows:Chapter 1 — About This Manual. Gives an overview of all three volumes of the Intel Archi-tecture Software Developer’s Manual. It also describes the notational conventions in thesemanuals and lists related Intel manuals and documentation of interest to programmers and hard-ware designers.Chapter 2 — Instruction Format. Describes the machine-level instruction format used for allIntel Architecture instructions and gives the allowable encodings of prefixes, the operand-iden-tifier byte (ModR/M byte), the addressing-mode specifier byte (SIB byte), and the displacementand immediate bytes.Chapter 3 — Instruction Set Reference. Describes each of the Intel Architecture instructionsin detail, including an algorithmic description of operations, the effect on flags, the effect ofoperand- and address-size attributes, and the exceptions that may be generated. The instructions 1-1
  19. 19. ABOUT THIS MANUALare arranged in alphabetical order. The FPU, MMX™ Technology instructions, and StreamingSIMD Extensions are included in this chapter.Appendix A — Opcode Map. Gives an opcode map for the Intel Architecture instruction set.Appendix B — Instruction Formats and Encodings. Gives the binary encoding of each formof each Intel Architecture instruction.Appendix C — Compiler Intrinsics and Functional Equivalents. Gives the Intel C/C++compiler intrinsics and functional equivalents for the MMX™ Technology instructions andStreaming SIMD Extensions.1.2. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTUREThe contents of the Intel Architecture Software Developer’s Manual, Volume 1, are as follows:Chapter 1 — About This Manual. Gives an overview of all three volumes of the Intel Archi-tecture Software Developer’s Manual. It also describes the notational conventions in thesemanuals and lists related Intel manuals and documentation of interest to programmers and hard-ware designers.Chapter 2 — Introduction to the Intel Architecture. Introduces the Intel Architecture and thefamilies of Intel processors that are based on this architecture. It also gives an overview of thecommon features found in these processors and brief history of the Intel Architecture.Chapter 3 — Basic Execution Environment. Introduces the models of memory organizationand describes the register set used by applications.Chapter 4 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stackand the mechanisms provided for making procedure calls and for servicing interrupts andexceptions.Chapter 5 — Data Types and Addressing Modes. Describes the data types and addressingmodes recognized by the processor.Chapter 6 — Instruction Set Summary. Gives an overview of all the Intel Architectureinstructions except those executed by the processor’s floating-point unit. The instructions arepresented in functionally related groups.Chapter 7 — Floating-Point Unit. Describes the Intel Architecture floating-point unit,including the floating-point registers and data types; gives an overview of the floating-pointinstruction set; and describes the processor’s floating-point exception conditions.Chapter 8 — Programming with Intel MMX™ Technology. Describes the Intel MMX™technology, including registers and data types, and gives an overview of the MMX™ technologyinstruction set.Chapter 9 — Programming with the Streaming SIMD Extensions. Describes the IntelStreaming SIMD Extensions, including the registers and data types.1-2
  20. 20. ABOUT THIS MANUALChapter 10 — Input/Output. Describes the processor’s I/O architecture, including I/O portaddressing, the I/O instructions, and the I/O protection mechanism.Chapter 11 — Processor Identification and Feature Determination. Describes how to deter-mine the CPU type and the features that are available in the processor.Appendix A — EFLAGS Cross-Reference. Summarizes how the Intel Architecture instruc-tions affect the flags in the EFLAGS register.Appendix B — EFLAGS Condition Codes. Summarizes how the conditional jump, move, andbyte set on condition code instructions use the condition code flags (OF, CF, ZF, SF, and PF) inthe EFLAGS register.Appendix C — Floating-Point Exceptions Summary. Summarizes the exceptions that can beraised by floating-point instructions.Appendix D — SIMD Floating-Point Exceptions Summary. Provides the Streaming SIMDExtensions mnemonics, and the exceptions that each instruction can cause.Appendix E — Guidelines for Writing FPU Exception Handlers. Describes how to designand write MS-DOS* compatible exception handling facilities for FPU and SIMD floating-pointexceptions, including both software and hardware requirements and assembly-language codeexamples. This appendix also describes general techniques for writing robust FPU exceptionhandlers.Appendix F — Guidelines for Writing SIMD-FP Exception Handlers. Provides guidelinesfor the Streaming SIMD Extensions instructions that can generate numeric (floating-point)exceptions, and gives an overview of the necessary support for handling such exceptions.1.3. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDEThe contents of the Intel Architecture Software Developer’s Manual, Volume 3, are as follows:Chapter 1 — About This Manual. Gives an overview of all three volumes of the Intel Archi-tecture Software Developer’s Manual. It also describes the notational conventions in thesemanuals and lists related Intel manuals and documentation of interest to programmers and hard-ware designers.Chapter 2 — System Architecture Overview. Describes the modes of operation of an IntelArchitecture processor and the mechanisms provided in the Intel Architecture to support oper-ating systems and executives, including the system-oriented registers and data structures and thesystem-oriented instructions. The steps necessary for switching between real-address andprotected modes are also identified.Chapter 3 — Protected-Mode Memory Management. Describes the data structures, registers,and instructions that support segmentation and paging and explains how they can be used toimplement a “flat” (unsegmented) memory model or a segmented memory model. 1-3
  21. 21. ABOUT THIS MANUALChapter 4 — Protection. Describes the support for page and segment protection provided inthe Intel Architecture. This chapter also explains the implementation of privilege rules, stackswitching, pointer validation, user and supervisor modes.Chapter 5 — Interrupt and Exception Handling. Describes the basic interrupt mechanismsdefined in the Intel Architecture, shows how interrupts and exceptions relate to protection, anddescribes how the architecture handles each exception type. Reference information for eachIntel Architecture exception is given at the end of this chapter.Chapter 6 — Task Management. Describes the mechanisms the Intel Architecture provides tosupport multitasking and inter-task protection.Chapter 7 — Multiple Processor Management. Describes the instructions and flags thatsupport multiple processors with shared memory, memory ordering, and the advanced program-mable interrupt controller (APIC).Chapter 8 — Processor Management and Initialization. Defines the state of an Intel Archi-tecture processor and its floating-point and SIMD floating-point units after reset initialization.This chapter also explains how to set up an Intel Architecture processor for real-address modeoperation and protected- mode operation, and how to switch between modes.Chapter 9 — Memory Cache Control. Describes the general concept of caching and thecaching mechanisms supported by the Intel Architecture. This chapter also describes thememory type range registers (MTRRs) and how they can be used to map memory types of phys-ical memory. MTRRs were introduced into the Intel Architecture with the Pentium® Proprocessor. It also presents information on using the new cache control and memory streaminginstructions introduced with the Pentium® III processor.Chapter 10 — MMX™ Technology System Programming. Describes those aspects of theIntel MMX™ technology that must be handled and considered at the system programming level,including task switching, exception handling, and compatibility with existing system environ-ments. The MMX™ technology was introduced into the Intel Architecture with the Pentium®processor.Chapter 11 — Streaming SIMD Extensions System Programming. Describes those aspectsof Streaming SIMD Extensions that must be handled and considered at the system programminglevel, including task switching, exception handling, and compatibility with existing systemenvironments. Streaming SIMD Extensions were introduced into the Intel Architecture with thePentium® processor.Chapter 12 — System Management Mode (SMM). Describes the Intel Architecture’s systemmanagement mode (SMM), which can be used to implement power management functions.Chapter 13 — Machine-Check Architecture. Describes the machine-check architecture,which was introduced into the Intel Architecture with the Pentium® processor.Chapter 14 — Code Optimization. Discusses general optimization techniques for program-ming an Intel Architecture processor.Chapter 15 — Debugging and Performance Monitoring. Describes the debugging registersand other debug mechanism provided in the Intel Architecture. This chapter also describes thetime-stamp counter and the performance-monitoring counters.1-4
  22. 22. ABOUT THIS MANUALChapter 16 — 8086 Emulation. Describes the real-address and virtual-8086 modes of the IntelArchitecture.Chapter 17 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit codemodules within the same program or task.Chapter 18 — Intel Architecture Compatibility. Describes the programming differencesbetween the Intel 286™, Intel386™, Intel486™, Pentium®, and P6 family processors. Thedifferences among the 32-bit Intel Architecture processors (the Intel386™, Intel486™,Pentium®, and P6 family processors) are described throughout the three volumes of the IntelArchitecture Software Developer’s Manual, as relevant to particular features of the architecture.This chapter provides a collection of all the relevant compatibility information for all IntelArchitecture processors and also describes the basic differences with respect to the 16-bit IntelArchitecture processors (the Intel 8086 and Intel 286 processors).Appendix A — Performance-Monitoring Events. Lists the events that can be counted withthe performance-monitoring counters and the codes used to select these events. Both Pentium®processor and P6 family processor events are described.Appendix B — Model-Specific Registers (MSRs). Lists the MSRs available in the Pentium®and P6 family processors and their functions.Appendix C — Dual-Processor (DP) Bootup Sequence Example (Specific to Pentium®Processors). Gives an example of how to use the DP protocol to boot two Pentium® processors(a primary processor and a secondary processor) in a DP system and initialize their APICs.Appendix D — Multiple-Processor (MP) Bootup Sequence Example (Specific to P6 FamilyProcessors). Gives an example of how to use of the MP protocol to boot two P6 family proces-sors in a MP system and initialize their APICs.Appendix E — Programming the LINT0 and LINT1 Inputs. Gives an example of how toprogram the LINT0 and LINT1 pins for specific interrupt vectors.1.4. NOTATIONAL CONVENTIONSThis manual uses special notation for data-structure formats, for symbolic representation ofinstructions, and for hexadecimal numbers. A review of this notation makes the manual easierto read.1.4.1. Bit and Byte OrderIn illustrations of data structures in memory, smaller addresses appear toward the bottom of thefigure; addresses increase toward the top. Bit positions are numbered from right to left. Thenumerical value of a set bit is equal to two raised to the power of the bit position. Intel Archi-tecture processors are “little endian” machines; this means the bytes of a word are numberedstarting from the least significant byte. Figure 1-1 illustrates these conventions. 1-5
  23. 23. ABOUT THIS MANUAL Data Structure Highest 24 23 16 15 8 7 0 Bit offset 31 Address 28 24 20 16 12 8 4 Lowest Byte 3 Byte 2 Byte 1 Byte 0 0 Address Byte Offset Figure 1-1. Bit and Byte Order1.4.2. Reserved Bits and Software CompatibilityIn many register and memory layout descriptions, certain bits are marked as reserved. Whenbits are marked as reserved, it is essential for compatibility with future processors that softwaretreat these bits as having a future, though unknown, effect. The behavior of reserved bits shouldbe regarded as not only undefined, but unpredictable. Software should follow these guidelinesin dealing with reserved bits:• Do not depend on the states of any reserved bits when testing the values of registers which contain such bits. Mask out the reserved bits before testing.• Do not depend on the states of any reserved bits when storing to memory or to a register.• Do not depend on the ability to retain information written into any reserved bits.• When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register. NOTE Avoid any software dependence upon the state of reserved bits in Intel Archi- tecture registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.1-6
  24. 24. ABOUT THIS MANUAL1.4.3. Instruction OperandsWhen instructions are represented symbolically, a subset of the Intel Architecture assemblylanguage is used. In this subset, an instruction has the following format:label: mnemonic argument1, argument2, argument3where:• A label is an identifier which is followed by a colon.• A mnemonic is a reserved name for a class of instruction opcodes which have the same function.• The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the opcode. When present, they take the form of either literals or identifiers for data items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items declared in another part of the program (which may not be shown in the example).When two operands are present in an arithmetic or logical instruction, the right operand is thesource and the left operand is the destination.For example:LOADREG: MOV EAX, SUBTOTALIn this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX isthe destination operand, and SUBTOTAL is the source operand. Some assembly languages putthe source and destination in reverse order.1.4.4. Hexadecimal and Binary NumbersBase 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed bythe character H (for example, F82EH). A hexadecimal digit is a character from the followingset: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by thecharacter B (for example, 1010B). The “B” designation is only used in situations where confu-sion as to the type of number might arise.1.4.5. Segmented AddressingThe processor uses byte addressing. This means memory is organized and accessed as asequence of bytes. Whether one or more bytes are being accessed, a byte address is used tolocate the byte or bytes of memory. The range of memory that can be addressed is called anaddress space. 1-7
  25. 25. ABOUT THIS MANUALThe processor also supports segmented addressing. This is a form of addressing where aprogram may have many independent address spaces, called segments. For example, a programcan keep its code (instructions) and stack in separate segments. Code addresses would alwaysrefer to the code space, and stack addresses would always refer to the stack space. The followingnotation is used to specify a byte address within a segment:Segment-register:Byte-addressFor example, the following segment address identifies the byte at address FF79H in the segmentpointed by the DS register:DS:FF79HThe following segment address identifies an instruction address in the code segment. The CSregister points to the code segment and the EIP register contains the address of the instruction.CS:EIP1.4.6. ExceptionsAn exception is an event that typically occurs when an instruction causes an error. For example,an attempt to divide by zero generates an exception. However, some exceptions, such as break-points, occur under other conditions. Some types of exceptions may provide error codes. Anerror code reports additional information about the error. An example of the notation used toshow an exception and error code is shown below.#PF(fault code)This example refers to a page-fault exception under conditions where an error code naming atype of fault is reported. Under some conditions, exceptions which produce error codes may notbe able to report an accurate code. In this case, the error code is zero, as shown below for ageneral-protection exception.#GP(0)Refer to Chapter 5, Interrupt and Exception Handling, in the Intel Architecture Software Devel-oper’s Manual, Volume 3, for a list of exception mnemonics and their descriptions.1-8
  26. 26. ABOUT THIS MANUAL1.5. RELATED LITERATUREThe following books contain additional material related to Intel processors:• Intel Pentium® II Processor Specification Update, Order Number 243337-010.• Intel Pentium® Pro Processor Specification Update, Order Number 242689.• Intel Pentium® Processor Specification Update, Order Number 242480.• AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618.• AP-578, Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors, Order Number 242415-001.• Pentium® Pro Processor Family Developer’s Manual, Volume 1: Specifications, Order Number 242690-001.• Pentium® Processor Family Developer’s Manual, Order Number 241428.• Intel486™ Microprocessor Data Book, Order Number 240440.• Intel486™ SX CPU/Intel487™ SX Math Coprocessor Data Book, Order Number 240950.• Intel486™ DX2 Microprocessor Data Book, Order Number 241245.• Intel486™ Microprocessor Product Brief Book, Order Number 240459.• Intel386™ Processor Hardware Reference Manual, Order Number 231732.• Intel386™ Processor System Software Writers Guide, Order Number 231499.• Intel386™ High-Performance 32-Bit CHMOS Microprocessor with Integrated Memory Management, Order Number 231630.• 376 Embedded Processor Programmer’s Reference Manual, Order Number 240314.• 80387 DX User’s Manual Programmer’s Reference, Order Number 231917.• 376 High-Performance 32-Bit Embedded Processor, Order Number 240182.• Intel386™ SX Microprocessor, Order Number 240187.• Microprocessor and Peripheral Handbook (Vol. 1), Order Number 230843.• AP-528, Optimizations for Intel’s 32-Bit Processors, Order Number 242816-001. 1-9
  27. 27. ABOUT THIS MANUAL1-10
  28. 28. 2Instruction Format
  29. 29. CHAPTER 2 INSTRUCTION FORMATThis chapter describes the instruction format for all Intel Architecture processors.2.1. GENERAL INSTRUCTION FORMATAll Intel Architecture instruction encodings are subsets of the general instruction format shownin Figure 2-1. Instructions consist of optional instruction prefixes (in any order), one or twoprimary opcode bytes, an addressing-form specifier (if required) consisting of the ModR/M byteand sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), and an immediatedata field (if required). Instruction Opcode ModR/M SIB Displacement Immediate Prefixes Up to four 1 or 2 byte 1 byte 1 byte Address Immediate prefixes of opcode (if required) (if required) displacement data of 1-byte each of 1, 2, or 4 1, 2, or 4 (optional) bytes or none bytes or none 7 65 32 0 7 6 5 3 2 0 Reg/ Mod Opcode R/M Scale Index Base Figure 2-1. Intel Architecture Instruction Format2.2. INSTRUCTION PREFIXESThe instruction prefixes are divided into four groups, each with a set of allowable prefix codes:• Lock and repeat prefixes. — F0H—LOCK prefix. — F2H—REPNE/REPNZ prefix (used only with string instructions). — F3H—REP prefix (used only with string instructions). — F3H—REPE/REPZ prefix (used only with string instructions). — F3H—Streaming SIMD Extensions prefix. 2-1
  30. 30. INSTRUCTION FORMAT• Segment override. — 2EH—CS segment override prefix. — 36H—SS segment override prefix. — 3EH—DS segment override prefix. — 26H—ES segment override prefix. — 64H—FS segment override prefix. — 65H—GS segment override prefix.• Operand-size override, 66H• Address-size override, 67HFor each instruction, one prefix may be used from each of these groups and be placed in anyorder. The effect of redundant prefixes (more than one prefix from a group) is undefined andmay vary from processor to processor.• Streaming SIMD Extensions prefix, 0FHThe nature of Streaming SIMD Extensions allows the use of existing instruction formats.Instructions use the ModR/M format and are preceded by the 0F prefix byte. In general, opera-tions are not duplicated to provide two directions (i.e. separate load and store variants). For moreinformation, see Section B.4.1., “Instruction Prefixes” in Appendix B, Instruction Formats andEncodings.2.3. OPCODEThe primary opcode is either 1 or 2 bytes. An additional 3-bit opcode field is sometimes encodedin the ModR/M byte. Smaller encoding fields can be defined within the primary opcode. Thesefields define the direction of the operation, the size of displacements, the register encoding,condition codes, or sign extension. The encoding of fields in the opcode varies, depending onthe class of operation.2.4. MODR/M AND SIB BYTESMost instructions that refer to an operand in memory have an addressing-form specifier byte(called the ModR/M byte) following the primary opcode. The ModR/M byte contains threefields of information:• The mod field combines with the r/m field to form 32 possible values: eight registers and 24 addressing modes.• The reg/opcode field specifies either a register number or three more bits of opcode infor- mation. The purpose of the reg/opcode field is specified in the primary opcode.• The r/m field can specify a register as an operand or can be combined with the mod field to encode an addressing mode.2-2
  31. 31. INSTRUCTION FORMATCertain encodings of the ModR/M byte require a second addressing byte, the SIB byte, to fullyspecify the addressing form. The base-plus-index and scale-plus-index forms of 32-bitaddressing require the SIB byte. The SIB byte includes the following fields:• The scale field specifies the scale factor.• The index field specifies the register number of the index register.• The base field specifies the register number of the base register.Refer to Section 2.6. for the encodings of the ModR/M and SIB bytes.2.5. DISPLACEMENT AND IMMEDIATE BYTESSome addressing forms include a displacement immediately following either the ModR/M orSIB byte. If a displacement is required, it can be 1, 2, or 4 bytes.If the instruction specifies an immediate operand, the operand always follows any displacementbytes. An immediate operand can be 1, 2, or 4 bytes.2.6. ADDRESSING-MODE ENCODING OF MODR/M AND SIB BYTESThe values and the corresponding addressing forms of the ModR/M and SIB bytes are shown inTables 2-1 through 2-3. The 16-bit addressing forms specified by the ModR/M byte are in Table2-1, and the 32-bit addressing forms specified by the ModR/M byte are in Table 2-2. Table 2-3shows the 32-bit addressing forms specified by the SIB byte.In Tables 2-1 and 2-2, the first column (labeled “Effective Address”) lists 32 different effectiveaddresses that can be assigned to one operand of an instruction by using the Mod and R/M fieldsof the ModR/M byte. The first 24 give the different ways of specifying a memory location; thelast eight (specified by the Mod field encoding 11B) give the ways of specifying the generalpurpose, MMX™ technology, and SIMD floating-point registers. Each of the register encodingslist five possible registers. For example, the first register-encoding (selected by the R/M fieldencoding of 000B) indicates the general-purpose registers EAX, AX or AL, the MMX™ tech-nology register MM0, or the SIMD floating-point register XMM0. Which of these five registersis used is determined by the opcode byte and the operand-size attribute, which select either theEAX register (32 bits) or AX register (16 bits).The second and third columns in Tables 2-1 and 2-2 gives the binary encodings of the Mod andR/M fields in the ModR/M byte, respectively, required to obtain the associated effective addresslisted in the first column. All 32 possible combinations of the Mod and R/M fields are listed.Across the top of Tables 2-1 and 2-2, the eight possible values of the 3-bit Reg/Opcode field arelisted, in decimal (sixth row from top) and in binary (seventh row from top). The seventh row islabeled “REG=”, which represents the use of these three bits to give the location of a secondoperand, which must be a general-purpose register, an MMX™ technology register, or a SIMDfloating-point register. If the instruction does not require a second operand to be specified, thenthe 3 bits of the Reg/Opcode field may be used as an extension of the opcode, which is repre- 2-3
  32. 32. INSTRUCTION FORMATsented by the sixth row, labeled “/digit (Opcode)”. The five rows above give the byte, word, anddoubleword general-purpose registers; the MMX™ technology registers; the Streaming SIMDExtensions registers; and SIMD floating-point registers that correspond to the register numbers,with the same assignments as for the R/M field when Mod field encoding is 11B. As with theR/M field register options, which of the five possible registers is used is determined by theopcode byte along with the operand-size attribute.The body of Tables 2-1 and 2-2 (under the label “Value of ModR/M Byte (in Hexadecimal)”)contains a 32 by 8 array giving all of the 256 values of the ModR/M byte, in hexadecimal. Bits3, 4 and 5 are specified by the column of the table in which a byte resides, and the row specifiesbits 0, 1 and 2, and also bits 6 and 7.2-4

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