Published on

  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide


  1. 1. SoC, PSoC, & SoPC Design J. Hamblen
  2. 2. SoC, PSoC, & SoPC Design <ul><li>Design a single chip solution </li></ul><ul><li>Recent option for Embedded Systems </li></ul><ul><li>System on a Chip (SoC) – one chip replaces a embedded system board </li></ul><ul><li>System on a Programmable Chip (SoPC) is an SoC that uses a large FPGA </li></ul><ul><li>Intellectual Property (IP) cores are used to provide processors and common hardware for SoPC designs. IP cores are drop in design elements purchased from another vendor </li></ul>
  3. 3. eBox 2300- SoC Embedded PC
  4. 4. eBox 2300 – SoC example <ul><li>Same I/O features as a standard PC motherboard </li></ul><ul><li>Uses a Vortex 86 SOC X86 Processor </li></ul><ul><li>Motherboard Chipset is in the Processor chip </li></ul><ul><li>Boots from Flash memory – Notebook disk optional </li></ul><ul><li>No cooling fan needed and small size 4.5 by 4.5 inch </li></ul><ul><li>X86 processor is slower than PC’s processor </li></ul><ul><li>Low cost $150 and runs Windows XP and CE </li></ul><ul><li>Used in ECE 4180, several 4007 design projects and Windows Embedded student design contest </li></ul>
  5. 5. SoC ASIC Design <ul><li>Design an single chip Application Specific Integrated Circuit (ASIC) solution for the product </li></ul><ul><li>ASIC Advantages </li></ul><ul><ul><li>Faster clock speed </li></ul></ul><ul><ul><li>Lowest cost for very high volume parts </li></ul></ul><ul><ul><ul><li>1,000,000 transistors for <$.25 </li></ul></ul></ul>
  6. 6. ASIC Disadvantages <ul><li>Long lead time to develop an ASIC </li></ul><ul><ul><li>Several months or perhaps years </li></ul></ul><ul><ul><li>Requires complex Legal Agreements with ASIC fab house and for any IP cores needed </li></ul></ul><ul><ul><li>Can increase time to market </li></ul></ul><ul><li>Designer must develop complete testing methods </li></ul><ul><li>Increasing Mask and Design Costs </li></ul><ul><ul><li>Up to $50,000,000 for a state-of-the-art submicron ASIC </li></ul></ul><ul><ul><li>High product volume needed to support mask and large engineering development cost – need up to $250,000,000 in chip sales to recover these costs (5X development cost) </li></ul></ul>
  7. 7. PSoC Design <ul><li>Programmable System on a Chip (PSoC) </li></ul><ul><li>A small low-cost microcontroller with on chip memory, some programmable logic, and mixed signal hardware (A/D) – single chip solution </li></ul><ul><li>Tools provided to configure hardware, and then write software in assembly or C </li></ul><ul><li>Also has a new Labview type development tool </li></ul><ul><li>Limited to just tens of KBs of on chip memory – so no OS or full networking support </li></ul><ul><li>PSoC is a trademark of Cypress </li></ul><ul><li>PSoC II – new 32-bit ARM based processor core </li></ul>
  8. 8. Low Cost Cypress PSoC Board
  9. 9. SoPC Design <ul><li>Use a large Field Programmable Gate Array (FPGA) with a processor IP core </li></ul><ul><li>In a Soft IP core logic elements from the FPGA are used to build the processor. </li></ul><ul><li>In a Hard IP core a full custom VLSI layout for the processor is placed in the FPGA </li></ul><ul><li>Soft cores more flexible, but have slower clock rates </li></ul>
  10. 10. Processor Cores for SoPC <ul><li>Soft Processor Cores for FPGAs </li></ul><ul><ul><li>NIOS II - Altera </li></ul></ul><ul><ul><li>Microblaze, Picoblaze, 8051 - Xilinx </li></ul></ul><ul><li>Hard Processor Cores for FPGAs </li></ul><ul><ul><li>MIPS Altera, also ARM but not on newest FPGAs </li></ul></ul><ul><ul><li>PowerPC Xilinx, but not on newest FPGAs </li></ul></ul><ul><ul><li>S5 Tensilica Xtensa - Stretch </li></ul></ul><ul><li>Largest FPGAs can support several processors on a single FPGA chip </li></ul><ul><li>Cost as low as $.35 per processor </li></ul>
  11. 11. Software for SoPC Design <ul><li>Traditional FPGA tools (VHDL & Verilog) </li></ul><ul><ul><li>FPGA also used to build additional hardware </li></ul></ul><ul><li>Processor Configuration Tool (Soft Cores) </li></ul><ul><li>C/C++ Compiler for Processor Program Code </li></ul><ul><li>Tools to debug code and load memories </li></ul><ul><li>Optional OS support for Processor </li></ul><ul><li>Board Support Package (BSP) provides OS I/O device drivers for a specific board design </li></ul>
  12. 12. FPGA-based SOPC CAD Tool Flow
  13. 13. FEATURES OF COMMERCIAL SOFT PROCESSOR CORES Feature Nios 3.1 MicroBlaze 3.2 Datapath 16 or 32 bits 32 bits Pipeline Stages 5 3 Frequency up to 150 MHz up to 150 MHz Gate Count 26,000–40,000 30,000–40,000 Register File up to 512 32 general purpose (window size: 32) and 32 special purpose Instruction Word 16 bits 32 bits Instruction Cache Optional Optional Hardware Multiplier Optional Optional This clock speed is not achievable on all devices. Some devices limit the maximum frequency to as low as 50 MHz.
  14. 14. Processor IP Core configuration tool for Altera’s Nios Processor
  15. 15. SOPC Memory Organization Non-volatile (Flash) Memory is used both to boot processor software at power on and to configure the FPGA hardware
  16. 16. SoPC Design Space
  17. 17. Hardware Software Tradeoffs
  18. 18. Combining both approaches <ul><li>Add custom co-processor for main processor </li></ul><ul><li>Add custom instructions to processor </li></ul><ul><li>Perform high data rate calculations in hardware and the rest in software </li></ul><ul><li>Automatic C compilers that transform critical inner loop code to hardware are available – Stretch Inc ( ) and recently from major FPGA Vendors. </li></ul>
  19. 19. Nios II C-to-Hardware Acceleration Compiler – C2H <ul><li>Automatic acceleration of ANSI/ISO C code </li></ul><ul><li>GHz performance possible with mW power consumption  </li></ul><ul><li>Tight integration with software design flow </li></ul><ul><li>Direct connection of hardware accelerators to CPU's memory map </li></ul><ul><li>Seamless support for pointers and arrays </li></ul><ul><li>Efficient latency-aware scheduling and pipelining of memory transactions </li></ul>
  20. 20. Hardware Accelerator Design Flow
  21. 21. Block Diagram of example Mandelbot Processor System
  22. 22. Effect of Adding Hardware Accelerators on System Performance (left) and Power Consumption (right)
  23. 23. Effects of Reducing System Clock Frequency
  24. 24. Other C2H Benchmarks <ul><li>Algorithm Speedup Hardware Increase </li></ul><ul><li>Autocorrelation 41.0x 115 Mhz 124% </li></ul><ul><li>Bit Allocation 42.3x 110 Mhz 152% </li></ul><ul><li>Convolution 13.3x 95 Mhz 133% </li></ul><ul><li>FFT 15.0x 85 Mhz 208% </li></ul><ul><li>High Pass Filter 42.9x 110 Mhz 181% </li></ul><ul><li>Matrix Rotate 73.6x 95 Mhz 106% </li></ul><ul><li>RGB to CMYK 41.5x 120 Mhz 84% </li></ul><ul><li>RGB to YIQ 39.9x 110 Mhz 158% </li></ul>
  25. 25. Recent SoPC OS Developments <ul><li>FPGA processors initially did not have an MMU for Virtual Memory – Limits OS choices (Xilinx & Altera have just announced an MMU core and full Linux should soon follow) </li></ul><ul><li>Linux, Nucleus PLUS, NORTi, Wind River VxWorks AE X, OSE RTOS, and KROS are available for Altera’s FPGAs </li></ul><ul><li>Linux, QNX Neutrino, Wind River, & uC/OS-II RTOS are available for Xilinx’s FPGAs </li></ul>
  26. 26. Recent Trends <ul><li>Increased mask costs and long product development times are making ASICs very expensive </li></ul><ul><li>Fewer ASIC Design Starts for last 10 years </li></ul><ul><li>An industry survey in 2009 showed 30X more FPGA-based design starts than ASICs </li></ul>
  27. 27. SoPC Technology Tradeoffs <ul><li>Feature SOPC ASIC Fixed-Microprocessor </li></ul><ul><li>S/W Flexibility    </li></ul><ul><li>H/W Flexibility    </li></ul><ul><li>Reconfigurability    </li></ul><ul><li>Development Cost    </li></ul><ul><li>Peripheral Costs    </li></ul><ul><li>Performance    </li></ul><ul><li>Production Cost   [1]  </li></ul><ul><li>Power Efficiency    </li></ul><ul><li>Legend :  – Good;  – Moderate;  – Poor </li></ul>[1] In very large quantities.
  28. 28. Altera’s SoPC UP 3 board contains a 200,000 gate FPGA with Flash and SRAM memory. It can run a soft Nios II RISC processor IP core
  29. 29. Xilinx SOPC FPGA Board
  30. 30. Xilinx SOPC Board Features <ul><li>Xilinx Virtex-2 Pro FPGA with 3M Logic Gates, 136 18-bit multipliers for DSP applications, 2,448Kb of internal SRAM, and two PowerPC Microprocessors </li></ul><ul><li>DDR SDRAM DIMM that can accept up to 2Gbytes of RAM </li></ul><ul><li>10/100 Ethernet port & USB 2.0 port </li></ul><ul><li>Non-volatile Flash memory & Compact Flash card slot </li></ul><ul><li>VGA Video port & PC Audio Codec </li></ul><ul><li>Serial ATA, PS/2, & RS-232 ports </li></ul><ul><li>High and Low Speed I/O expansion connectors with a large collection of available expansion boards </li></ul><ul><li>Low cost: Board is $299 for Universities </li></ul><ul><li>Xilinx SOPC Development tools are free for Universities </li></ul>
  31. 31. Altera’s SoPC DE2 board contains a large FPGA with hardware multiply, 4MB Flash, and 8MB SDRAM memory. It can run C code on a soft Nios II RISC processor IP core
  32. 32. This R/C hobbyist Hummer was converted to an autonomous robot with vision tracking capabilities using a SOPC board and a CMUCAM
  33. 33. This Amigobot commercial robot was originally designed to be remotely controlled using a PC with a serial cable. An FPGA-based SOPC board was added to control the robot autonomously .
  34. 34. Altera DE2 board running uClinux on NIOS II processor (uClinux has no MMU)
  35. 35. A student designed FPGA-based SOPC board with FLASH and SRAM inside a modified toy front loader used as a robot.
  36. 36. A small SOPC-based aircraft autopilot system that contains an FPGA with a Nios processor core, a DSP processor, and memory. The bottom sensor board contains a GPS receiver, an A/D converter, MEMS gyros and accelerometers for all three axes, an airspeed sensor, and an altitude sensor. Photograph ©2004 Henrik Christophersen
  37. 37. Autopilot bottom sensor I/O board contains a GPS receiver, an A/D converter, MEMS gyros and accelerometers for all three axes, an airspeed sensor, and an altitude sensor. Photograph ©2004 Henrik Christophersen
  38. 41. Seismic Mine Detection System
  39. 42. SoPC Prototype with Sensors in Laboratory Experimental Model Analog Sensors Digital Sensors FPGA SoPC Board Seismic Source
  40. 43. Conclusions <ul><li>SoPC is at the leading edge of electronic systems design </li></ul><ul><li>Opportunities exist for innovative design approaches using processors, memory, and programmable FPGA logic </li></ul><ul><li>OS support is available for FPGA processors </li></ul><ul><li>New approaches and new tools are needed to explore and develop designs </li></ul>