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  • We will cover NAND flash memory in this talk.
  • This figure shows the organization of a typical NAND flash memory. NAND flash memory is specially designed for data storage, because it has a better ratio of capacity and price. The memory space is partition into blocks, and each block is of a fixed number of pages. When we erase, we erase one block. When we read and write, we read and write on page. Typically, there are 32 pages in a block.
  • Flash memory is write-once, bulk-erasing. And It has a limited lifetime for each block. We shall illustrate the characteristics by example.
  • First, according to the cell interconnection fashion, flash memory can be classified into NAND and NOR types. Because of the higher cost, byte-addressing capability, and lower write performance, NOR-type flash is used to store codes as an XIP medium; On the contrary, NAND-type flash is used to store the data, as a replacement of hard disks.
  • Small block flash memory has smaller page and block sizes, and its performance is worse than the large block flash memory. Therefore, small block flash are replaced with large block flash now.
  • SLC flash stores single bit in each flash memory cell, and MLC stores multiple bits in a cell. MLC trades for lower production cost and higher chip density with lower performance, cell endurance, and additional operational constraints. As a consequence, MLC is now widely used in low-end commercial applications, where SLC is used in industrial and high-end commercial products.
  • Here, as we can see, Flash memory has different properties against HD. The write-once property, the bulk-erase constraint, and the limited endurance all make the behaviors of flash different. Completely different.
  • Because of the unique properties of flash memory mentioned above, flash memory requires careful management to yield better performance and reliability. On the bottom of the storage hierarchy, the MTD layer provides uniform interface for accessing & controlling the flash memory HW. Then, the management schemes can be implemented on the device-side, as the FTL; or the host-side, as Device Driver or the Native File Systems. While the device-side solutions have very limited computation resources such as the processing power and the RAM buffer, the Host-Side solutions requires the support from OS and FS and have less portability and compatibility.
  • A typical Flash Memory Management Scheme comprises [Each component explained briefly]
  • There are several views of flash memory storage systems. The user-view primarily concerns about [ 照念 ] , while the architecture-view concerns about [ 照念 ] , and The HW-view concerns about [ 照念 ]
  • There are already a large number of flash memory benchmarks on the market. [QUICK!!!!]
  • Thus, a more complete behavior analysis is necessary
  • Our goal is to provide users and architects with a fair comparison scheme for flash memory storage systems.
  • Our behavior analysis scheme includes micro-benchmark and macro-benchmark. The micro-benchmark evaluate specific metrics, and macro-benchmark evaluate actual, macroscopic overall performance of the system. Each of the tests will be explained later. Note that Best response time and worst throughput are not measured here because [REASON]
  • Because many FTL implementation favors sequential accesses, it is reasonable to evaluate the maximum bandwidth provided by the device.
  • With similar ideas, a completely small random accesses with random starting address and 1-sector length can exploit the worst-case response time for accesses.
  • To evaluate the overheads brought by the read disturbance effect. We should repetitively read to a small portion of data to trigger read disturbance effect. However, because of the FS cache, OS cache, FTL cache or driver cache’s caching effects, additional read operations to other irrelevant data should be inserted to fill the cache to eliminate the caching effects.
  • Similarly, to evaluate the overheads of FTL on managing write disturbance effects, we should repetitive write to small portions of data. Irrelevant accesses are also inserted to flush the caches.
  • For multimedia applications, the contents of the media is accessed sequentially, while the metadata (including the FS metadata and FTL metadata) are accessed randomly. Thus, we design the access trace as the combination of random accesses to hot data and sequential accesses to cold data, as shown here.
  • Large number of unknown applications  normally distributed access pattern
  • In summary, we have proposed a fair evaluation strategy for flash memory storage systems, Such that Users can compare various flash products Designers can evaluate different designs
  • Here’s my contact information.
  • Thank you.
  • slides

    1. 1. The Behavior Analysis of Flash Memory Storage Systems Po-Chun Huang , Yuan-Hao Chang, Tei-Wei Kuo, Jen-Wei Hsieh Dept. of Comp. Sci. & Info. Engr. National Taiwan University, Taiwan
    2. 2. Agenda <ul><li>Introduction </li></ul><ul><li>Flash-Memory Characteristics </li></ul><ul><li>Behavior Analysis </li></ul><ul><li>Conclusion </li></ul>April 15, 2010
    3. 3. Introduction – Why Flash Memory <ul><li>Diversified Application Domains </li></ul>April 15, 2010 Mobile Media Players Solid-State Disks (SSD) Thumb Disks Multimedia Memory Cards Embedded Systems
    4. 4. Introduction – NAND-Type Flash Makers!4B94B7453D4BFD9E!988.entry Source: iSuppli Corp (Unit: Million Dollars) [EE Times,11/30/2007] NAND flash prices have dropped by an average of more than 40 % per year.
    5. 5. Flash Memory Characteristics – A Typical Architecture …… Block 0 Block 1 Block 2 Block 3 Erase one block 1 Page = 2KB 1 Block = 64 pages(128KB) …… Write one page
    6. 6. Flash Memory Characteristics – Access Constraints <ul><li>Write-Once </li></ul><ul><ul><li>No writing on the same page unless its residing block is erased! </li></ul></ul><ul><ul><li>Pages are classified into valid , invalid , and free pages. </li></ul></ul><ul><li>Bulk-Erasing </li></ul><ul><ul><li>Pages are erased in a block unit to recycle used but invalid pages. </li></ul></ul><ul><li>Wear-Leveling </li></ul><ul><ul><li>Each block has a limited lifetime in erasing counts. </li></ul></ul>
    7. 7. Flash Memory Characteristics – NOR-type & NAND-type April 15, 2010 NOR-type NAND-type Access Unit Byte (Random Read, Sequential Write) Page (Serial Access) Cost Higher Lower XIP Support Yes No Write 8MB/s 20MB/s Purpose XIP media (such as EPROM, EEPROM, EAROM, and DRAM) Nonvolatile secondary storage media (such as Hard disk)
    8. 8. Flash Memory Characteristics – Small and Large Block Flash Memory <ul><li>Flash memory page and block sizes are growing </li></ul>April 15, 2010 Small Block Large Block Page Size 512+16 Bytes 2K~8K Bytes Block Size 16K Bytes 128K~256K Bytes Used for... <1G Bytes >1G Bytes Throughput Low High Small Block Now Switches to Large Block
    9. 9. Introduction (cont’d) Single-Level-Cell and Multi-Level Cell Flash Memory <ul><li>MLC has gained its momentum in cost and capacity! </li></ul>April 15, 2010 *Write-Erase Cycles SLC Flash MLC Flash Cell Level 1 2 or 4 Cost 17.2 USD / 16G Bytes 5.25 USD / 16G Bytes Chip Density Lower Higher Access Speed Higher Lower Average Cell Endurance 10 4 ~10 5 W-E cycles* 10 3 ~10 4 W-E cycles Partial Programming Yes (4 times) No (1 time) Sequential Utilization Constraint of Pages in a Block No Yes
    10. 10. Flash-Memory Characteristics – Hard Disks versus Flash Memory April 15, 2010 Hard Disk (NAND-type) Flash Memory Access Granularity Page-based Access Page-based Access Write-once No Yes Erasure No Need to Erase Bulk Erasure Medium Lifetime Very Long Median Cost Lower Higher Other Properties and Constraints <ul><li>Long seek time and rotational latency </li></ul><ul><li>Power-hunger </li></ul><ul><li>Spin-up latency </li></ul><ul><ul><li>Shock resistance </li></ul></ul><ul><ul><li>High density </li></ul></ul>
    11. 11. Flash-Memory Characteristics – System Architecture <ul><li>In order to address the special properties and constraints of flash memory, a good management scheme is required </li></ul><ul><li>Typical forms of management schemes are implemented as the Flash Translation Layer ( FTL ), the driver , or the Flash File System ( FFS ), each with different design considerations </li></ul>April 15, 2010
    12. 12. Flash-Memory Characteristics – System Architecture <ul><li>A Typical Flash Memory Management Scheme </li></ul>April 15, 2010 Perform Address Translation from LBA to PBA Determine the Physical Position of Written Data Because of the Write-Once Property, We Must Perform Garbage Collection Task to Released the Space Occupied by Invalidated Data Garbage Collector Requires This Facility Even the Times of Utilization of Each Block to Avoid Fast Corruption
    13. 13. Behavior Analysis – Motivation <ul><li>Physical properties of flash memory are very different from those of hard drives. </li></ul><ul><li>The management schemes give flash-memory storage systems special behaviors, compared to in-place update policies of many other storage systems. </li></ul><ul><li>There are few benchmarking tools with the considerations of the physical properties and the management schemes of flash memory. </li></ul>April 15, 2010
    14. 14. Behavior Analysis – Motivation <ul><li>Views of a Flash Memory Storage System </li></ul>April 15, 2010 User-Perspective Architecture-Perspective Hardware-Perspective Operation response time or throughput, product functional life span, file system operation latencies, prices, and compatibility Maintenance resources, assembly costs, architecture, and mediation between user expectation, hardware functions, and the flash management scheme production costs, materials, technology, cell reliability, etc.
    15. 15. Behavior Analysis – Motivation <ul><li>Revisiting of Existing I/O benchmarks </li></ul><ul><ul><li>IOZone : a file system benchmark considering no flash properties ( ) </li></ul></ul><ul><ul><li>IOMeter : synthetic benchmark that users can control the degree of random-sequential access mixture . Does not consider flash properties ( ) </li></ul></ul><ul><ul><li>The effective I/O bandwidth benchmark : examine the I/O bandwidth achievable of an I/O device ( ) </li></ul></ul><ul><ul><li>IOBench : An operating system and processor independent synthetic input/output (IO) benchmark designed to put a configurable IO and processor (CP) load on the system under test ( ) </li></ul></ul><ul><ul><li>Bonnie++ : a benchmark suite that is aimed at performing a number of simple tests of hard drive and file system performance ( ) </li></ul></ul>April 15, 2010
    16. 16. Behavior Analysis – Motivation <ul><li>Unfortunately, </li></ul><ul><ul><li>Physical properties of flash memory are different from hard drives </li></ul></ul><ul><ul><li>There are few benchmarking tools including the consideration of the management schemes of flash memory storage systems </li></ul></ul><ul><ul><li>All previous works are based on user-perspective and consider no flash-specific properties and management overheads </li></ul></ul>April 15, 2010
    17. 17. Behavior Analysis <ul><li>We need an evaluation strategy considering both the user and system architecture’s perspectives , so that </li></ul><ul><ul><li>Users can fairly evaluate the cost-effectiveness of various flash products </li></ul></ul><ul><ul><li>System architects can have a fair method to evaluate their designs on architectures or the flash management schemes </li></ul></ul>April 15, 2010
    18. 18. The Behavior Analysis <ul><li>Our Approach </li></ul><ul><ul><li>Micro-benchmark : evaluate specific metrics (instead of the overall status) of the system </li></ul></ul><ul><ul><ul><li>Best-case throughput </li></ul></ul></ul><ul><ul><ul><li>Worst-case response time </li></ul></ul></ul><ul><ul><li>Macro-benchmark : probe the actual macroscopic behaviors of the systems </li></ul></ul><ul><ul><ul><li>Read disturbance effects </li></ul></ul></ul><ul><ul><ul><li>Write disturbance effects </li></ul></ul></ul><ul><ul><ul><li>Simulation of actual traces </li></ul></ul></ul>April 15, 2010
    19. 19. The Behavior Analysis <ul><li>Best-Case Throughput Test : It is to examine the maximum possible performance of the device </li></ul><ul><ul><li>Large, sequential accesses yield the best performance on many FTLs </li></ul></ul>April 15, 2010 i th access LBA Largest request packet length (1024 sectors on Windows; 128 sectors on USB interface)
    20. 20. The Behavior Analysis <ul><li>Worst-Case Response Time Test : It is to examine the real-time access capability of a device </li></ul><ul><ul><li>Small, random accesses yield the worst performance on many FTLs </li></ul></ul>April 15, 2010 LBA i th access
    21. 21. The Behavior Analysis <ul><li>Read-Disturb Effect Test : It is to test the management overheads about the read-disturb effect </li></ul><ul><ul><li>Repetitively read a small range of data to examine the write disturbance overhead </li></ul></ul><ul><ul><li>The first phase is only used to write the data that will be read later </li></ul></ul>April 15, 2010 LBA i th access Phase-1 (Preparation) Phase-2 (Actual Test) Hot area (test area) Write the data for Future Read Monitor the Performance Drop Continuously Fill the Cache with Irrelevant Data to Avoid the Caching Effects
    22. 22. The Behavior Analysis <ul><li>Write-Disturb Effect Test : It is to test the management overheads about the write-disturb effect </li></ul><ul><ul><li>Repetitively write to a small range of data to examine the write-disturb overhead </li></ul></ul><ul><ul><li>Accesses to other addresses are used to eliminate the caching effect </li></ul></ul>April 15, 2010 LBA i th access Hot area (test area) Hot area (test area)
    23. 23. The Behavior Analysis <ul><li>Multimedia environment : multimedia cards, thumb disks, and SSDs are often used to keep multimedia contents </li></ul><ul><ul><li>The contents of audio or video files are generally sequentially accessed, while their metadata are randomly accessed </li></ul></ul>April 15, 2010 i th access LBA Metadata Area ( Randomly Accessed) Data Area ( Sequentially Accessed) Similar to the Behaviors of FAT
    24. 24. The Behavior Analysis <ul><li>Multiplexed environment : A large number of different applications mixed together in multi-purpose systems </li></ul><ul><ul><li>The behaviors are affected by a large number of factors, forming a pattern following normal distribution </li></ul></ul>April 15, 2010 LBA i th access Random Starting Address Random Access Length
    25. 25. About the Timing of Request Issuing <ul><li>The time intervals between consecutive requests matters </li></ul><ul><ul><li>Foreground management </li></ul></ul><ul><ul><ul><li>Handle the requests on-demand </li></ul></ul></ul><ul><ul><ul><li>Introduce user-sensible delays </li></ul></ul></ul><ul><ul><li>Background management </li></ul></ul><ul><ul><ul><li>Handle some management tasks on system idle time </li></ul></ul></ul><ul><ul><ul><li>Is not always applicable; for example, read requests must be served on-demand </li></ul></ul></ul><ul><li>If the interval between requests is large, background management will yield better performance, while foreground won’t </li></ul>April 15, 2010
    26. 26. Conclusion and Future Work <ul><li>Conclusion </li></ul><ul><ul><li>In this paper, we provide a fair evaluation strategy for flash memory storage systems so that </li></ul></ul><ul><ul><ul><li>Users can evaluate the cost-effectiveness of various flash products </li></ul></ul></ul><ul><ul><ul><li>Designers can evaluate the pros and cons of their designs and improve them </li></ul></ul></ul><ul><li>Future Work </li></ul><ul><ul><li>Investigate the relationship among different access patterns , system architectures , and flash memory management schemes </li></ul></ul><ul><ul><li>Analysis the access patterns of various applications of flash memory in the next generation </li></ul></ul>April 15, 2010
    27. 27. Contact Information <ul><li>Po-Chun Huang, Ph.D. Student </li></ul><ul><ul><li>Advisor : Prof. Tei-Wei Kuo </li></ul></ul><ul><ul><li>Mail & MSN : [email_address] </li></ul></ul><ul><ul><li>Flash Research Group : </li></ul></ul><ul><ul><li>Office : +886-2-33664888#438 </li></ul></ul><ul><ul><li>Fax : +886-2-23628167 </li></ul></ul><ul><ul><li>Address : </li></ul></ul><ul><li>Dept. of Computer Science & Information Engr. </li></ul><ul><li>National Taiwan University, Taipei, Taiwan 106 </li></ul>April 15, 2010
    28. 28. <ul><li>Q & A </li></ul>April 15, 2010