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  • Hello my name is Olivier Ginez and I ‘m going to present you the main problematic of my thesis that I have started 4 months ago : “ The Contribution to find New Test Methodologies for Embedded and Stacked Flash Memories “ This Thesis is a collaboration between ATMEL Rousset company and LIRMM (the Microelectronic Laboratory of Montpellier)  
  • The agenda of my speech is composed of : A general Introduction Then, I will introduce you the principle and the physical mechanisms in a Floating Gate The different Flash Architectures that you can find Later I will speak about The beginning of Faults modeling and Testing approach for Flash Memories I will develop around the Core-cell defect and Faults , and about particular Coupling Fault and Disturbance due to the Flash architecture Finally, I will ask : “Can we use the RAM modeling and Testing Background ?” Then, I will close my speech by a diagram that presents the direction to take to find solution in Flash Testing and objectives of my Thesis
  • There are many Non Volatile Memories which are widely used like ROM, EPROM but our study is based only on Flash Memories. Flash Mems are Electrically, Erasable and Programmable. Flash Mems present lot of advantages and drawbacks: Naturally the non volatile behaviour is an enormous advantage because it allows to store data without power supply during many years. Also, there are the Low Power Consumption and the Low Cost per Bit. However, there are some drawbacks like Reliability and Low programming time. This two points are more and more studied to make Flash more suitable for all applications.
  • I will introduce you some notions about the Floating Gate Technology. At first you must know that there is no Floating Gate standard. It’s according to each Company. There are two concepts of Floating Gate, the 1 st one is FLOTOX / ETOX where the charges are stored in a Polysilicon Floating Gate The 2 nd is MNOS / SONOS technology, it’s an insulator which catches the charges. To build his Flash memories, ATMEL uses the widely used FLOTOX concept. Just for Information, the difference between FLOTOX and ETOX is mainly the depth of tunnel oxide between Transistor Channel and Floating Gate. There exist 2 main effects to Write and Erase a Floating Gate: by Tunnelling Effect or Hot Electron Injection . In the next slides I will more detail the Fowler-Nordheim Tunnelling Effect on the actually ATMEL Flash cell.
  • Here, you can see the way to program a Floating Gate Using proper high voltage combination, you induce tunnelling effect through oxide. That way, you trap or evacuate charges in the floating gate. According to the charge quantity, you module the threshold voltage of the cell. The cell memory behaves like a standard transistor with a threshold voltage. This threshold varies following the state’s cell, from written to erased. You have realized a Non Volatile memory cell !!!
  • The Core-Cell is composed of: *Select Gate is used to isolate the core-cell when the cell is not selected -> to avoid disturbance of high voltage on the Bit Line *Control Gate, it’s the core-cell which has the floating gate to catch or liberate the electrons You can see on this slide the different voltages that we apply, and where we apply them, to create a Tunnelling effect. On the scheme you also see the charge way according to the voltage level.
  • To read cells, it’s very simple: When the Cell is erased, its threshold voltage is high and when you apply Vsense the cell delivers no current   When a Cell is written, its threshold is low and when Vsense is applied to the cell, she provides a little current (approximately 10uA). You can read this current thanks to the sense amplifier and then deduce the logical cell’s state.  
  • There are two main architectures in Flash Design: - NOR design which is used for speed up applications - And NAND used for mass data storage up to 1Gbits From an architecture point of view: - In NOR, on the same bit line the cells are placed in parallel, each one has a Bit Line contact - In NAND,here the c ells are placed by strings, each string has a Bit Line contact and can be made until thirty two serial cells. The cells strings are placed between select gates to minimize disturbance. As you will understand, the using of one or the other depends on the application that you will realize.
  • There are two main architectures in Flash Design: - NOR design which is used for speed up applications - And NAND used for mass data storage up to 1Gbits From an architecture point of view: - In NOR, on the same bit line the cells are placed in parallel, each one has a Bit Line contact - In NAND,here the c ells are placed by strings, each string has a Bit Line contact and can be made until thirty two serial cells. The cells strings are placed between select gates to minimize disturbance. As you will understand, the using of one or the other depends on the application that you will realize.
  • There are two main architectures in Flash Design: - NOR design which is used for speed up applications - And NAND used for mass data storage up to 1Gbits From an architecture point of view: - In NOR, on the same bit line the cells are placed in parallel, each one has a Bit Line contact - In NAND,here the c ells are placed by strings, each string has a Bit Line contact and can be made until thirty two serial cells. The cells strings are placed between select gates to minimize disturbance. As you will understand, the using of one or the other depends on the application that you will realize.
  • There are two main architectures in Flash Design: - NOR design which is used for speed up applications - And NAND used for mass data storage up to 1Gbits From an architecture point of view: - In NOR, on the same bit line the cells are placed in parallel, each one has a Bit Line contact - In NAND,here the c ells are placed by strings, each string has a Bit Line contact and can be made until thirty two serial cells. The cells strings are placed between select gates to minimize disturbance. As you will understand, the using of one or the other depends on the application that you will realize.
  • There are two main architectures in Flash Design: - NOR design which is used for speed up applications - And NAND used for mass data storage up to 1Gbits From an architecture point of view: - In NOR, on the same bit line the cells are placed in parallel, each one has a Bit Line contact - In NAND,here the c ells are placed by strings, each string has a Bit Line contact and can be made until thirty two serial cells. The cells strings are placed between select gates to minimize disturbance. As you will understand, the using of one or the other depends on the application that you will realize.
  • Now I’m going to present you the first reflection in Flash Faults Modeling. In a first time we have to focalize towards one Core Cell of the memory Array. Do not treat the peripheral circuitry and control logic around Core Cell The schematic that you can see, is an example of ATMEL Embedded Flash Core-Cell. Sprinkled in an exhaustive way some defects on the Core Cell like Bridges, Open, Short Circuits and analyse defects impact on the Memory Functional behaviour. Is the Cell stuck At or stuck open ? Which Functions are inhibited ? Read / Write Erase I repeat that it’s an exhaustive analyse and perhaps not realistic !!!! We must treat all possibilities …..      
  • To illustrate the previous slide, I have chosen to realize Open Defect Analysis on ATMEL embedded Core Cell. In the table, we can see the localisation of defects and its consequences on the cell’s state. We can also see the different actions which are inhibited by the Open Circuit. (Erase / Read / Write) These information allow to build patterns for Open Circuit detection . This Reflection Scheme will be apply to the new ATMEL Core-Cell technology and for all defects as possible.
  • Due to the presence of High Voltage during programming some cells of the memory and because of topological proximity between cells: We can observe some disturbances.   This disturb has a writing or erasing effect on unselected cells which share the same Bit Line or Word Line that the targeted one. The physical phenomenon of disturb can be Tunnelling Effect or Hot Electron Injection between Floating and Control Gate or between Floating Gate and the Transistor Channel. The Disturb is very complex because when we speak about it the notion of cycling is often mentioned. The cycling corresponds to a number of Write / Erase in a given time. The Disturb often implies the loss of Data in the floating Gate.  
  • Due to the presence of High Voltage during programming some cells of the memory and because of topological proximity between cells: We can observe some disturbances.   This disturb has a writing or erasing effect on unselected cells which share the same Bit Line or Word Line that the targeted one. The physical phenomenon of disturb can be Tunnelling Effect or Hot Electron Injection between Floating and Control Gate or between Floating Gate and the Transistor Channel. The Disturb is very complex because when we speak about it the notion of cycling is often mentioned. The cycling corresponds to a number of Write / Erase in a given time. The Disturb often implies the loss of Data in the floating Gate.  
  • Due to the presence of High Voltage during programming some cells of the memory and because of topological proximity between cells: We can observe some disturbances.   This disturb has a writing or erasing effect on unselected cells which share the same Bit Line or Word Line that the targeted one. The physical phenomenon of disturb can be Tunnelling Effect or Hot Electron Injection between Floating and Control Gate or between Floating Gate and the Transistor Channel. The Disturb is very complex because when we speak about it the notion of cycling is often mentioned. The cycling corresponds to a number of Write / Erase in a given time. The Disturb often implies the loss of Data in the floating Gate.  
  • Due to the presence of High Voltage during programming some cells of the memory and because of topological proximity between cells: We can observe some disturbances.   This disturb has a writing or erasing effect on unselected cells which share the same Bit Line or Word Line that the targeted one. The physical phenomenon of disturb can be Tunnelling Effect or Hot Electron Injection between Floating and Control Gate or between Floating Gate and the Transistor Channel. The Disturb is very complex because when we speak about it the notion of cycling is often mentioned. The cycling corresponds to a number of Write / Erase in a given time. The Disturb often implies the loss of Data in the floating Gate.  
  • Nowadays there are lot of studies lead by researcher and industrial, which treat RAM faults modeling and testing but nothings about Flash . The first reflection that I had when I started my thesis, has been: “ Why not based my work on the background of RAM testing? ” . It’s the reason why I have chosen to present this Slide. You can see the different Faults that you have on RAM memories . These faults are based on the Functional Diagram of a RAM, peripheral circuit and memory core-cell. In the majority of cases, the industrial methods to test RAM are March Test Strategies. This method allows to have a good coverage rate and an optimised testing time.
  • This comparison between RAM and Flash must be done with care because of the Functional Level Differences due to the Non Volatile behaviour of Flash. My first work is to analyse these differences and to deduce new models.   In another hand we saw that Industrials and Researcher use March Algorithms to RAM Testing. Because of the long time programming and erase mode by sector, this strategy isn’t suitable for Flash Testing. However, we can help ourselves with RAM Testing Approach to develop good Test Patterns for Flash Memories. There is still a long work around the fault modeling and test strategy to apply in Flash Context .
  • I think that this diagram represents the Brain way to converge to a New Efficiency Test Methodology for Flash Memories.   We must take into account the Flash architecture for the new ATMEL technology. Make an exhaustive fault analyse (Functional and Defect Oriented). Check the occurrence probability, and find different Models to simulate.   Before building Test Pattern or Test Algorithms strategy, we have to analyse the Flash functional constraint like programming time, read time, etc ….   Finally we will find an High Efficiency Test Methodology for Flash Testing and why not the development of BIST or BISD structures Thanks for your attention      
  • Servez vous

    1. 1. <ul><ul><li>Embedded Flash Memories Overviews </li></ul></ul><ul><ul><li>and Failures Analysis </li></ul></ul>Olivier GINEZ - PhD Student LIRM Montpellier/ ATMEL S.A.S Rousset MEET – Week 25
    2. 2. <ul><li>Flash Memories </li></ul><ul><ul><ul><ul><li>Introduction </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Technology </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Architectures </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Basic Building Blocks </li></ul></ul></ul></ul><ul><li>Flash Failure Mechanisms </li></ul><ul><ul><ul><ul><li>Hard Defects from Electrical View </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Hard Defects from Process View </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Dynamic Faults </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Resistive Shorts </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Disturbances and Soft Error </li></ul></ul></ul></ul><ul><li>Thesis Objectives </li></ul>OUTLINE
    3. 3. Flash Memories: Introduction (1) <ul><li>Non Volatile Memories Types: </li></ul><ul><ul><ul><li>ROM, EPROM, EEPROM and Flash (Electrically Erasable and Programmable) </li></ul></ul></ul><ul><li>Flash Characteristics: </li></ul><ul><ul><li>++ Non Volatile Behaviour (Store Data without Supply) </li></ul></ul><ul><ul><li>+ High Density ( particularly Flash NAND ) </li></ul></ul><ul><ul><li>+ Low Power Consumption </li></ul></ul><ul><ul><li>+ Low Cost per Bit (area, process, design) </li></ul></ul><ul><ul><li>+ Read Access Time </li></ul></ul><ul><ul><li>- Reliability, Endurance and Retention </li></ul></ul><ul><ul><li>-- Low Programming Time </li></ul></ul>
    4. 4. Flash Memories: Technology (1) <ul><li>No Standard </li></ul><ul><ul><ul><ul><li>Different Approaches according to </li></ul></ul></ul></ul><ul><ul><ul><ul><li>each Company </li></ul></ul></ul></ul><ul><li>Floating Gate Concept </li></ul><ul><ul><ul><ul><li>Flotox / Etox : Tunnelling through oxide </li></ul></ul></ul></ul><ul><ul><ul><ul><li>to conducting gate </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Mnos / Sonos : Trap e - within insulating </li></ul></ul></ul></ul><ul><ul><ul><ul><li>silicon nitride </li></ul></ul></ul></ul><ul><li>Write / Erase Mechanism </li></ul><ul><ul><ul><ul><li>Tunnelling Effect: “ Fowler-Nordheim” </li></ul></ul></ul></ul><ul><ul><ul><ul><li>HEI : “Hot Electron Injection” </li></ul></ul></ul></ul>
    5. 5. ETOX Cell with FN Tunnelling Program and Erase |Q FG | >> 0 |Q FG | = 0 V T adjusted by the charge in the floating gate Cell can be programmed in an analog way  I Tunnel =  * E² ox * exp (-  /E ox ) Flash Memories: Technology (2)
    6. 6. BN + Select Gate (WL) Control Gate GND BL VM 0 V VM VM VM 0V BL Control Gate Select Gate (WL) GND Tunnelling Effect ATMEL Embedded Flash Core-Cell VM : High Voltage to program (~14 to 17V) Flash Memories: Technology (3) VM 0 VM WRITE 0 (written) 0 VM VM WRITE 1 (erased) BL Control Gate Select Gate MODE
    7. 7. BN + Select Gate (WL) Control Gate GND BL Vsense Vdd 1V BL Control Gate Select Gate (WL) GND ATMEL Embedded Flash Core-Cell Vsense : Read Voltage  1v It’s a Current Sensing !! Vsense 1V Vdd Erased : Vt high  +2v => Icell= 0 Written : Vt low  -0.6v => Icell  0 Icell Flash Memories: Technology (4) 1v Vsense Vdd READ BL Control Gate Select Gate MODE
    8. 8. Serial Structure Parallel Structure BL 0 BL 1 WL 0 WL 1 n max => 32 Flash Memories: Architecture (1) <ul><li>NOR Architecture : </li></ul><ul><ul><li>Storage until 256Mbits </li></ul></ul><ul><ul><li>Random speed up access </li></ul></ul><ul><li>NAND Architecture: </li></ul><ul><ul><li>Growing faster than NOR memories market </li></ul></ul><ul><ul><li>Use for mass storage up to 1Gbits </li></ul></ul>BL 0 BL 1 WL 0 WL n-1 SG 0 SG 1
    9. 9. Flash Memories: Architecture (2) Random Read Fast Program Slow Random Read Slow Program Fast  1.22s/64Kbytes 33.6ms/64Kbytes Write + Delay 700ms/64Kbytes 8ms/64Kbytes Erase Delay 4.1ms/512bytes 8  s/byte 200  s/512bytes Write Delay 70ns parallel 25ns burst 50ns serial 25  s random Read Access Time 128 Mbits 512 Mbits Density NOR (ETOX) NAND
    10. 10. Flash Memories: Architecture (3) FLASH versus MRAM <1 20-30 Stand By Current (  A) >100mW 10- 30mW Dynamic Power 25-40ns 25ns Read Speed <10ns/bit 2ms/page Write Speed 47.3 16 Cell size F² 0.8 0.27 Cell size  m² 0.13 0.13 Technology  m 1T1MJT eMRAM (SPINTEC) 2T eFLOTOX (ATMEL)
    11. 11. Flash Memories: Basic Building Blocks (1)
    12. 12. Flash Memories: Basic Building Blocks (2)
    13. 13. Flash Failure Mechanisms: Hard Defects from Electrical View (1) BL j BL j+1 WL i WL i+1 Vss Vss WL i+2 2 1 3 4 3 1 Example of 2*3 bits Flash Memory Array Dual or Multiple Bit 4- Poly1 Short Not able to read some cell’s state (Read as stuck at 1’) 3- Contact Source Open Same state on bits of 2 adjacent Bit Lines 2- Metal 1 Bridge (Between BL i / BL i+1 ) Dual Bit at a logical ‘1’ (Not accessed) 1- Contact Open (On the Bit Line) Effect: Defect Types:
    14. 14. Flash Failure Mechanisms: Hard Defects from Process View (1) BN + Select Gate (WL) Control Gate N + N + 3 3 2 1 Cross Section of FLOTOX Core-Cell N + => Drop of HV BN + => Drop of HV 3- Junction Leakage No Charges Retention Single bit Failed 2- ONO Short (Interpoly Oxide) Too thick – No Program Effect Too thin – No Retention ≈ +Δtox (Å) - Bad Margin ≈ - Δtox (Å) - Bad Retention 1- Tunnel Window Effect: Defect Type:
    15. 15. Flash Failure Mechanisms: Dynamic Faults (1) <ul><li>Via on Strap Word Lines Opened : </li></ul><ul><ul><li>Access Time Increasing </li></ul></ul><ul><ul><li>Read Delay Fault (RDFs) </li></ul></ul>Straps to reduce resistive effects WL 0 BL 0 BL 2 BL 3 BL 1 Vref Poly2
    16. 16. Flash Failure Mechanisms: Resistive Shorts (1) <ul><li>Poly2 (Word Line) -> Metal1 (Bit Line) </li></ul>Targeted cells <ul><li>Defect 1 during Erasing WLi </li></ul><ul><li>Drop of HV and Bad Vt value on (i;j) </li></ul>2 1 4 3 Defect 2 during Writing cell(i,;j)  V BLj+1 switch from HZ to HV (+14v) Same Analysis for Poly2 (Word Line) / Poly2 (Sense gate) ! WL i WL i+1 Vss Vref i Vref i+1 BL j BL j+1 (i,j) (i+1,j) (i,j+1) (i+1,j+1)
    17. 17. Flash Failure Mechanisms: Disturb and Soft Error (1) * Programming Disturb 12volts <ul><li>Capacitive Coupling BL j / BL j+1 </li></ul><ul><li>V BLj = 12v * [C1 / (C1 + C2)] </li></ul><ul><li>Some measures have shown V BLj = 4v </li></ul><ul><li>Soft Programming of cell(i;j) !!! (remember I Tunnel equation) </li></ul><ul><li>Cell(i;j) logical state switching from ‘0’ to ‘1’ </li></ul><ul><li> My Functional Model is ‘BCPD’ (Bit Line Coupling Programming Disturb) </li></ul>BL j (HZ) BL j+1 Not selected cell Target Cell WL i ≈ 14v 0v C1 C2
    18. 18. Flash Failure Mechanisms: Disturb and Soft Error (2) * Reading Disturb HZ + <ul><li>Important I Leakage on the unselected cells with Vt low </li></ul><ul><li>Mask of Data to Read </li></ul><ul><li> NPSF (Neighborhood Pattern Sensitive Fault) </li></ul>0v BL j Vss 1.8v Vbl ≈ 1v Target Cell (a,j) 0v 0.7v I leak Vin Gnd 1 3 4 2 0 1 I leakage  0 I=0 To Sense Crosstalk Perturbation between 2 WL Subthreshold leakage  V gs = 0.1v   I ds1 = 10*I ds0
    19. 19. March Test Strategy Thesis Objectives: Flash versus RAM Testing (1) <ul><li>RAM Functional Faults: </li></ul><ul><ul><li>- Cells Stuck - RD/WR line Stuck </li></ul></ul><ul><ul><li>- CE line Stuck - Data Line Stuck or Open </li></ul></ul><ul><ul><li>- Pattern Sensitive - Wrong or Multiple Access </li></ul></ul><ul><ul><li>- Crosstalk on Data lines - Address Line Stuck or Open </li></ul></ul><ul><li>Simple Faults Models: </li></ul><ul><li>AFs / TFs / SAFs / SOFs / DRFs / BFs </li></ul><ul><li>Coupling Faults Models: </li></ul><ul><li>CFin / CFid / CFst / CFdst / NPSFs </li></ul>
    20. 20. Thesis Objectives: Flash versus RAM Testing (2) <ul><ul><ul><li>Flash Failure Mechanisms </li></ul></ul></ul><ul><ul><ul><li>Erase Mode by Sector </li></ul></ul></ul><ul><ul><ul><li>Programming Time is Longer </li></ul></ul></ul><ul><ul><ul><li>March Strategy not suitable </li></ul></ul></ul><ul><li>RAM Testing not Directly Applicable !! </li></ul>
    21. 21. « March tests for word-oriented memories » A.J. van de Goor – Delft University of Technology / Netherlands Thesis Objectives: Flash versus RAM Testing (3) <ul><li>Most of March are for Bit Oriented Memories: </li></ul><ul><ul><ul><ul><li>Nowadays not suitable ! </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Industrial Realities: </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Memories are Word Oriented (16/32/64…) </li></ul></ul></ul></ul></ul><ul><li>March Tests for Word Oriented Memories </li></ul><ul><ul><li>Modify Bit Oriented  March Algorithms: </li></ul></ul><ul><ul><ul><li>w 0 becomes w D and w 1 becomes w /D </li></ul></ul></ul><ul><ul><ul><li>r 0 becomes r D and r 1 becomes r /D </li></ul></ul></ul><ul><ul><ul><li>(with d = data background to apply on B bits Words ) </li></ul></ul></ul>
    22. 22. « March tests for word-oriented memories » A.J. van de Goor – Delft University of Technology / Netherlands Thesis Objectives: Flash versus RAM Testing (3) <ul><li>Inter-word faults </li></ul><ul><li> Hard fixed data background : </li></ul><ul><li>01010101 / 10101010 </li></ul><ul><li>Intra-word faults </li></ul><ul><li> Testing between cells in the same word </li></ul><ul><li> Example for CF disturb : </li></ul><ul><li> Nb D = 3 + 3*log 2 B with Nb D the number of different data backgrounds and B the number of bits contained in 1 word </li></ul>
    23. 23. 4 ms/page Thesis Objectives: Flash versus RAM Testing (4) <ul><li>Application to a Flash 64K * 32bits </li></ul><ul><ul><li>To optimize testing time we consider: </li></ul></ul><ul><ul><ul><ul><li> 1 page = 1 word 64*32 = 2048bits </li></ul></ul></ul></ul><ul><ul><li>D = 3 + 3*11 = 36 ( data backgrounds for the CF dst ) </li></ul></ul><ul><ul><li>Flash writing: </li></ul></ul><ul><ul><ul><ul><ul><li>Load </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Auto-Erase </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Functional Write-Word </li></ul></ul></ul></ul></ul><ul><li> Testing time = 1024*36*4ms = 147.5 sec </li></ul><ul><li> just for the CF dst intra-word testing ! </li></ul><ul><li>(1st order, Reading time is neglected ) </li></ul>
    24. 24. Memory Architecture Possible and Realistic Fault List Constraint linked to the Memory New Methodologies for Flash Testing Exhaustive Fault Analysis Thesis Objectives <ul><li>NAND or NOR </li></ul><ul><li>E 2 PROM or FLASH </li></ul><ul><li>NB Cells/Sector </li></ul><ul><li>Collect All Possible Faults </li></ul><ul><li>Fault Occurrence Probability </li></ul><ul><li>RAM like </li></ul><ul><li>Disturb Faults  </li></ul><ul><li>Write per Page </li></ul><ul><li>Read per Word </li></ul><ul><li>Programming Time </li></ul><ul><li>Optimized Algorithms </li></ul><ul><li>BIST and BISD </li></ul>
    25. 25. <ul><li>« March tests for word-oriented memories » </li></ul><ul><li>A.J. van de Goor – Delft University of Technology - Netherlands </li></ul><ul><li>«Crosstalk in Deep Submicron DRAMs » </li></ul><ul><li>Z. Yang, S. Mourad / Santa Clara University - USA / IEEE MTDT00 San Jose - USA </li></ul><ul><li>« Flash Memory: Technology-Driven Test » </li></ul><ul><li>J. Pineda de Gyvez, R. Beurze / Philips Eindhoven - Netherlands / ETW02 Corfu - Greece </li></ul><ul><li>« Diagonal Test and Diagnostic Schemes for Flash Memories » </li></ul><ul><li>S-K Chiu, J-C Yeh, C-T Huang, C-W Wu / LARC / NTHU - Taiwan </li></ul><ul><li>« RAMSES-FT: A fault simulator for Flash Memory Testing and Diagnostics » </li></ul><ul><li>S-K Chiu, J-C Yeh, C-T Huang, C-W Wu / LARC / NTHU - Taiwan </li></ul><ul><li>« Nonvolatile memory disturbs due to gate & junction leakage currents  » </li></ul><ul><li>J.E. Park 12 , J. Shields 3 , D.K. Schroder 2 / Solid-State Electronics 2002 </li></ul><ul><li>1 IBM - USA / 2 Arizona State University - USA / 3 Microchip Technology - USA </li></ul><ul><li>« EEPROM Memory: Threshold Voltage Built In Self Diagnosis  » </li></ul><ul><li>H. Aziza 12 , J.M Portal 1 , D. N é e 2 / IEEE ITC 2003 </li></ul><ul><li>1 L2MP Polytech’Marseille - France / 2 ST-Microelectronics Rousset - France </li></ul>Literature
    26. 26. <ul><li>« Semiconductor Memories: Technology, Testing and Reliability » </li></ul><ul><li>A-K.Sharma / IEEE Press, Piscataway, 1997 </li></ul><ul><li>« RAMSES-FT: A fault simulator for Flash Memory Testing and Diagnostics » </li></ul><ul><li>S-K Chiu, J-C Yeh, C-T Huang, C-W Wu / LARC / National Tsing Hua University </li></ul><ul><li>« Embedded EEPROM memories performance optimization  » </li></ul><ul><li>C. Papaix / ATMEL Rousset, France / LIRMM Montpellier / PhD Thesis 2002 </li></ul>Literature

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