Samsung Samsung NAND Flash Memory NAND Flash Memory

3,637 views

Published on

0 Comments
1 Like
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
3,637
On SlideShare
0
From Embeds
0
Number of Embeds
12
Actions
Shares
0
Downloads
133
Comments
0
Likes
1
Embeds 0
No embeds

No notes for slide

Samsung Samsung NAND Flash Memory NAND Flash Memory

  1. 1. Samsung NAND Flash Memory Memory Product & Technology Division 2000.3.15 Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  2. 2. NAND Flash Memory NAND Flash Memory Technology for Mass-Storage Technology for Mass-Storage n Non-volatile and Low Power Operation n Lowest Bit Cost Solid-State Memory Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  3. 3. Various Flash Memory Technologies Various Flash Memory Technologies Technology NOR DINOR T-Poly AND NAND Structure Program CHE F-N CHE F-N F-N Method Erase F-N F-N F-N F-N F-N Method Layers 2P2M 3P2M 3P1M 3P2M 2P1M Samsung Company Intel, AMD Mitsubishi SanDisk Hitachi Toshiba Reference : ISSCC 94, 95, 96 Flash Session Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  4. 4. Unit Cell Comparison Unit Cell Comparison Item NOR TYPE NAND TYPE Control Gate Control Gate Floating Gate Poly/ Poly Dielectric Floating Gate Tunnel Oxide Tunnel Oxide Vertical View N+ N- N+ N+ N+ N+ P-Substrate P-Substrate • One Tr. NMOS Floating Gate Device • One Tr. NMOS Floating Gate Device • Program : F-N Tunneling Features • Program : Hot - Electron • Erase : F-N Tunneling (No BTBT) • Erase : F-N Tunneling (BTBT Effect) • Low Vcc Possible Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  5. 5. Cell Architecture Comparison Cell Architecture Comparison NOR TYPE NAND TYPE • Large cell and fast random access • Small cell, but fast sequential access Bit Line Unit Bit Line Cell Contact 16 or 32 transistors Contact Common Source • Contact is the limiting factor for scale-down. • Easy to Scale Down. Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  6. 6. NOR Flash Erase Method NOR Flash Erase Method High Voltage Negative Gate Channel Erase Source Erase Source Erase GND -10V GND +12V - - - - Float +5V - - - - Float Float - - - - Float - - - - +Vera Key Factors : Device Scalability , Voltage Scalability (Vcc, Charge Pump), Maximum High Voltage, Current Consumption(BTBT), Reliability(P/E Endurance, Retention) Reference : 1. K. Yoshikawa.."Comparison of Current Flash EEPROM Erasing Methods .. " IEDM, pp.595-598, 1992. 2. K. Tamer San .. "Effects of Erase Source Bias on Flash EPROM Device Reliability," IEEE Trans. ED, vol.42, no. 1, pp.150-159, Jan. 1995. Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  7. 7. BTBT (Band To Band Tunneling) Effect BTBT (Band To Band Tunneling) Effect l During Erase Operation Vcg=0V l Gate Potential Assisted BTBT Phenomena Vs=12V l Increased Vs Current l Reliability Issues due to Hot-hole Trapping --> DD Structure for Source n References : 1. S. Haddad.. "Degradation Due to Hole Trapping in Flash Memory Cells," IEEE ED Letters, vol.10, no. 3, pp.117-119, March, 1989. 2. S. Keeny .."Complete Transient Simulation of Flash EEPROM Devices," IEEE Trans. ED, vol. 39, no. 12, pp.2750-2757, Dec. 1992. Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  8. 8. NOR Flash Program Method & Endurance NOR Flash Program Method & Endurance Program Method Typical Endurance Characteristics ~ 12V - - GND ~ 5V - - - - l Hot Electron Injection l Advantages . Fast Program Speed (~ us) l Disadvantages . Large Program Current (~500uA/cell) . Difficult Voltage Scaling . Strong Charge Pump Circuit for Low Vcc Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  9. 9. NAND Flash Program/ Erase Method NAND Flash Program/ Erase Method Program Erase 18 ~ 20V 0V Float - - Float Float - - - - Float - - - - - - 0V 19 ~ 21V l Use F-N Tunneling l Use F-N Tunneling l Channel Inversion l Channel Accumulation -> No DD Source (Easy Device Scaling) -> No BTBT Current (Easy Voltage Scaling) Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  10. 10. NAND Flash Endurance vs. Characteristics NAND Flash Endurance vs. Characteristics Cell Vth Shift Program/ Erase Time Variation 1.5 1.E+4 1.0 0.5 Programmed Cell 0.0 1.E+3 Erase Time -0.5 Cell Vth (V) Time ( uS) -1.0 -1.5 1.E+2 -2.0 -2.5 Erased Cell Program Time -3.0 -3.5 1.E+1 1.E0 1.E1 1.E2 1.E3 1.E4 1.E5 1.E6 1.E7 1.E+0 1.E+2 1.E+4 1.E+6 Number of P/E Cycles Number of P/E Cycles Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  11. 11. NAND Flash Operation NAND Flash Operation • Address map 128+4Mb ARRAY I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 1’st cycle A0 A1 A2 A3 A4 A5 A6 A7 2’nd cycle A9 A10 A11 A12 A13 A14 A15 A16 128Mb 1 Block (=32 Page) 3’rd cycle A17 A18 A19 A20 A21 A22 A23 *X : 32KRow (16K+512) Byte (1024 Block) A0 ~ A7 : Selects the starting address of the 1st half of the register A9 ~ A13 : Selects 1 page of 1 block (32 pages) A14 ~ A23 : Selects 1 of 1024 blocks • Read Operation CLE 512 Column 16 Column 1 Slow Row CE access WE Page Register ALE (512+16Byte) RE 1st 2nd 3rd Dout N Dout N+1 Dout 528 2 Fast Page Access I/O0 - 7 2 R/B Command,address and data multiplexed into I/O port 1 downloaded from array to page register Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  12. 12. NAND Flash Performance Analysis NAND Flash Performance Analysis ms Time calculation for updating 160KB file 300 263(ms) 260(ms) 80 80 200 140(ms) 119(ms) Erase time 40 20 100 Program time 160 160 88 88 Read time 22.8 19.8 11.5 10.5 0 8Mb 16Mb 16Mb 32/64Mb 32/64Mb 128Mb 128Mb Page size 256Byte 256Byte 512Byte 512Byte Block size 4KByte 4KByte 8KByte 16KByte Read/page 10us 10us 10/7us 10us Program/page 250us 250us 250/200us 200us Erase/block 2ms 2ms 2ms 2ms Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  13. 13. Bit Cost Forecast of NAND Flash Bit Cost Forecast of NAND Flash Cost($/MB) $2 128Mb 256Mb $1 512Mb 1999 2000 2001 2002 Year n Bit cost continues to be dropped as the memory density grows. Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS
  14. 14. Flash Memory Application Segment Flash Memory Application Segment Chip Storage (Mbit) Applications Key Features 1 2 4 8 16 32 64 128 256 EPROM Replacement Random Access - PC BIOS Firmware - Separate Add./Data Line - OS/APPS Software - Chip or Large Erase Block - D.Cellular Phone - 1 piece/system - Boot Code Storage Mass Storage Low Cost - PCMCIA ATA Card - High Speed Sequential - Solid-State Disk Access - Digital Still Camera - Mid./Small Block Size - Digital Audio Recorder - Single Voltage(3V) - Music Player Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS

×