Quantum Dot Applications for
    Flash Memory, Semiconductor
      Lasers, and Photodetectors
                 Sanjay Bane...
How do you save flash memory?
     Improve the tunneling oxide layer
        Increase capacitance and reduce accidental
  ...
Quantum dots and high-K tunneling
     oxide reduce size, increase stability
Adding a high-K tunneling oxide layer and qua...
High-K devices have high endurance

                                                1.2
                                  ...
High-K layer improves charge retention

                           0



                           5
        Charge Loss [...
Protein templates fix quantum dot
       arrangement problems
Quantum dots as used
today are not optimally
distributed
Cur...
High-K and quantum dots create
           better distinction of states

                         0.7       HfO2 tunneling ...
Mobility layer improves programming
     speed and reduces power needed
Flash memory cell with high-mobility channel

    ...
Technology overview
Specialty proteins enable precise distribution
and size control of nanoparticles on a surface
  Improv...
Next steps
Current status
  3 patent applications filed
  Bench prototype complete
Next steps to commercialization
  Proto...
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Quantum Dot Applications for Quantum Dot Applications for ...

  1. 1. Quantum Dot Applications for Flash Memory, Semiconductor Lasers, and Photodetectors Sanjay Banerjee Department of Electrical and Computer Engineering Microelectronics Research Center Flash memory is failing to track with Moore’s Law Current fabrication and materials have inherent size limitations which are becoming critical Reduction in the tunneling oxide layer leads to fragility and cell failure beyond 80 angstroms Programming problems Speed High voltage and power required Retention Precision/distinguishability 2 1
  2. 2. How do you save flash memory? Improve the tunneling oxide layer Increase capacitance and reduce accidental quantum tunneling Replace the floating gate Prevent accidental discharge Find methods to improve programmability Increase channel mobility Improve materials to increase speed, retention, lower voltage, lower power 3 Failure rates increase as you shrink current tunneling oxide layers Standard flash memory cell Control gate Control oxide Floating gate Tunneling oxide n+ Source Drain n+ 4 2
  3. 3. Quantum dots and high-K tunneling oxide reduce size, increase stability Adding a high-K tunneling oxide layer and quantum dots Si-Ge-C and Control gate metal nanocrystal Control oxide floating gate High-K tunneling oxide n+ Source Drain n+ 5 High-K tunneling layer Replace current materials with a high-K tunneling oxide: Lowers voltage and power to program Improves retention of charge (thicker layers) Increases capacitance Can increase thickness without reducing programmability Reduces quantum tunneling leakage 6 3
  4. 4. High-K devices have high endurance 1.2 HfO2 1.0 Program Threshold Voltage(V) 0.8 Erase 0.6 Program 0.4 Erase 0.2 SiO2 0.0 0 1 2 3 4 5 6 10 10 10 10 10 10 10 Number of Cycles 7 High-K layer makes programming and erase faster 0.4 HfO2 tunneling oixde =4.8nm SiO2 tunneling oxide = 3.6nm Program HfO2 2.5V Threshold Voltage shift (V) 0.2 SiO2 4V 0.0 SiO2 4V -0.2 Erase HfO2 2.5V -0.4 -3 -2 -1 0 1 2 10 10 10 10 10 10 Program/Erase Time (s) 8 4
  5. 5. High-K layer improves charge retention 0 5 Charge Loss [%] 10 SiO2 tunneling oxide (3.6nm) 15 HfO2 tunneling oxide (4.8nm) 20 0 1 2 3 4 10 10 10 10 10 Time (s) 9 Quantum dots avoid failure problems Use of independently charged quantum dot nanocrystals replacing the floating gate later With current continuous layers, one flaw discharges the entire cell With quantum dots, flaw only discharges dots immediately above the flaw, cell maintains charge Floating gate Tunneling oxide High-K tunneling oxide 10 5
  6. 6. Protein templates fix quantum dot arrangement problems Quantum dots as used today are not optimally distributed Currently randomly laid on top of the tunneling layer Using self-assembled chaperonin proteins to template nano- crystals 11 High-K layer and quantum dot gate features Accidental quantum tunnel discharges 4.00E-011 nn-Pb-3-6 (-8V/8V 500ms cycling) 3.50E-011 reduced 3.00E-011 2.50E-011 Programmability C(F) 2.00E-011 12-15 4 maintained 1.50E-011 1.00E-011 1 2 3 5.00E-012 0.00E+000 -2 -1 0 1 2 V(V) 12 6
  7. 7. High-K and quantum dots create better distinction of states 0.7 HfO2 tunneling oxide SiO2 tunneling oxide 0.6 Without dots 0.5 With SiGe dots ∆Vth(V) 0.4 0.3 0.2 Without dots 0.1 0.0 2 3 4 5 6 VCG(V) 13 How do you improve programmability? Standard flash memory cell Control gate Si-Ge-C and Control oxide metal nanocrystal Floating gate floating gate Tunneling oxide n+ Source Drain n+ 14 7
  8. 8. Mobility layer improves programming speed and reduces power needed Flash memory cell with high-mobility channel Control gate Si-Ge-C and Control oxide metal nanocrystal Floating gate floating gate Tunneling oxide n+ Source Drain n+ Buried SiGe heterostructure layer 15 We have invented a vastly improved memory cell Completed cell: high-K tunneling oxide layer, quantum dots, and mobility layer Si-Ge-C and Control gate metal nanocrystal Control oxide floating gate High-K tunneling oxide n+ Source Drain n+ Buried SiGe heterostructure layer 16 8
  9. 9. Technology overview Specialty proteins enable precise distribution and size control of nanoparticles on a surface Improves performance, reliability Reduces potential size Changing materials of tunneling layer: Improves reliability Increases capacity Improves programming Adding mobility layer Faster programming at lower voltages 17 Benefits and applications New technologies improve non-volatile flash memory Increased speed Reduced size of memory cell for portable devices Lower leakage currents for low-power portable and low- handheld applications Low-voltage/power, high-speed, high-reliability flash Low- high- high- memory for digital cameras, cell phones, etc. Protein template method has a variety of other applications Semiconductor lasers Photodetectors 18 9
  10. 10. Next steps Current status 3 patent applications filed Bench prototype complete Next steps to commercialization Prototype it in a memory circuit (as opposed to individual cells) Start-up opportunity! Follow-up meeting: Thursday, June 9, 2:30-3:30pm 19 10

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