Published on

1 Like
  • Be the first to comment

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide


  1. 1. Computer Organisation & Architecture IS C351 First Semester 2008-2009 Lecture #16-17 http://discovery.bits-pilani.ac.in/discipline/csis/virendra/isc351/coarc.htm <ul><li>What’s Next: </li></ul><ul><li>Semiconductor Main Memory </li></ul><ul><ul><li>Organization </li></ul></ul><ul><ul><li>DRAM and SRAM </li></ul></ul><ul><ul><li>Chip Logic </li></ul></ul><ul><ul><li>Module Organization </li></ul></ul><ul><li>Advanced DRAM organization </li></ul><ul><ul><li>Synchronous DRAM </li></ul></ul><ul><ul><li>DDR SDRAM </li></ul></ul><ul><ul><li>Cache DRAM </li></ul></ul>
  2. 2. Dynamic RAM <ul><li>Bits stored as charge in capacitors charges leak so need refreshing even when powered </li></ul><ul><li>Simpler construction and smaller per bit so less expensive </li></ul><ul><li>Slower operations, used for main memory </li></ul><ul><li>Address line active when bit read or written </li></ul><ul><ul><li>Transistor switch closed (current flows) </li></ul></ul><ul><li>Write </li></ul><ul><ul><li>Voltage to bit line (high for 1 low for 0) </li></ul></ul><ul><ul><li>Then signal address line </li></ul></ul><ul><ul><ul><li>Transfers charge to capacitor </li></ul></ul></ul><ul><li>Read </li></ul><ul><ul><li>Address line selected and transistor turns on </li></ul></ul><ul><ul><li>Charge from capacitor fed via bit line to sense amplifier </li></ul></ul><ul><ul><ul><li>Compares with reference value to determine 0 or 1. Capacitor charge must be restored </li></ul></ul></ul>
  3. 3. Static RAM <ul><li>Bits stored as on/off switches no charges to leak </li></ul><ul><li>No refreshing needed when powered </li></ul><ul><li>More complex construction so larger per bit and more expensive </li></ul><ul><li>Faster used for Cache </li></ul><ul><li>Transistor arrangement gives stable logic state </li></ul><ul><li>State 1 </li></ul><ul><ul><li>C 1 high, C 2 low, T 1 T 4 off, T 2 T 3 on </li></ul></ul><ul><li>State 0 </li></ul><ul><ul><li>C 2 high, C 1 low, T 2 T 3 off, T 1 T 4 on </li></ul></ul><ul><li>Address line transistors T 5 T 6 is switch </li></ul><ul><li>Write – apply value to B & compliment to B </li></ul><ul><li>Read – value is on line B </li></ul>
  4. 4. Read Only Memory (ROM) <ul><li>Permanent storage </li></ul><ul><ul><li>Nonvolatile </li></ul></ul><ul><li>Used for- </li></ul><ul><ul><li>Microprogramming (see later) </li></ul></ul><ul><ul><li>Library subroutines </li></ul></ul><ul><ul><li>Systems programs (BIOS) </li></ul></ul>
  5. 5. Types of ROM <ul><li>Written during manufacture </li></ul><ul><ul><li>Very expensive for small runs </li></ul></ul><ul><li>Programmable (once) </li></ul><ul><ul><li>PROM </li></ul></ul><ul><ul><li>Needs special equipment to program </li></ul></ul><ul><li>Read “mostly” </li></ul><ul><ul><li>Erasable Programmable (EPROM) </li></ul></ul><ul><ul><ul><li>Erased by UV </li></ul></ul></ul><ul><ul><li>Electrically Erasable (EEPROM) </li></ul></ul><ul><ul><ul><li>Takes much longer to write than read </li></ul></ul></ul><ul><ul><li>Flash memory </li></ul></ul><ul><ul><ul><li>Erase whole memory electrically </li></ul></ul></ul>
  6. 6. FF circuit Sense / Write Address decoder FF CS cells Memory circuit Sense / Write Sense / Write circuit Data input /output lines: A 0 A 1 A 2 A 3 W 0 W 1 W 15 b 7 b 1 b 0 W R / b  7 b  1 b  0 b 7 b 1 b 0 • • • • • • • • • • • • • • • • • • • • • • • • • • • Organization of 16X8 memory chip
  7. 7. 16x8 Memory Chip: Organization Details <ul><li>Organized in the form of an array, each cell is capable to store one bit of information </li></ul><ul><li>Each row of cells constitutes a memory word, and all cells are connected to a common line referred to as the word line, driven by the address decoder </li></ul><ul><li>Cells in each column are connected to a sense/write circuit by two bit lines </li></ul><ul><li>Stores 128 bits (16x8) and requires 14 external connections for address, data and control lines </li></ul>
  8. 8. Organization of a 1K  1 memory chip CS Sense / Write circuitry array memory cell address 5-bit row input/output Data 5-bit decoder address 5-bit column address 10-bit output multiplexer 32-to-1 input demultiplexer 32 32  W R / W 0 W 1 W 31 and How many external connections are required?
  9. 9. Memory Organisation Issues <ul><li>A 16Mbit chip can be organised as 1M of 16 bit words </li></ul><ul><ul><li>36 pins require to address </li></ul></ul><ul><ul><li>Chip size increases </li></ul></ul><ul><li>It can be organized as 2M x 8 </li></ul><ul><ul><li>29 pins are required to address </li></ul></ul><ul><li>It can be organised 1 bit per chip </li></ul><ul><ul><li>A 16Mbit chip can be organised as a 2048 x 2048 x 4 bit array </li></ul></ul><ul><ul><li>Reduces number of address pins </li></ul></ul><ul><ul><ul><li>Multiplex row address and column address </li></ul></ul></ul><ul><ul><ul><li>11 pins to address (2 11 =2048) </li></ul></ul></ul><ul><ul><ul><li>Adding one more pin doubles range of values so x4 capacity </li></ul></ul></ul>
  10. 10. Typical 16 Mb DRAM (4M x 4)
  11. 11. Packaging
  12. 12. 256kByte Module Organisation
  13. 13. 1MByte Module Organisation
  14. 14. Synchronous DRAM (SDRAM) <ul><li>Access is synchronized with an external clock </li></ul><ul><li>Address is presented to RAM </li></ul><ul><li>RAM finds data (CPU waits in conventional DRAM) </li></ul><ul><li>Since SDRAM moves data in time with system clock, CPU knows when data will be ready </li></ul><ul><li>CPU does not have to wait, it can do something else </li></ul><ul><li>Burst mode allows SDRAM to set up stream of data and fire it out in block </li></ul>
  15. 15. DDR SDRAM <ul><li>SDRAM can only send data once per clock </li></ul><ul><li>Double-data-rate SDRAM can send data twice per clock cycle </li></ul><ul><ul><li>Rising edge and falling edge </li></ul></ul><ul><li>Developed by Mitsubishi </li></ul><ul><li>Integrates small SRAM cache (16 kb) onto generic DRAM chip </li></ul><ul><li>Cache DRAM </li></ul><ul><li>Used as true cache </li></ul><ul><ul><li>64-bit lines </li></ul></ul><ul><ul><li>Effective for ordinary random access </li></ul></ul><ul><li>To support serial access of block of data </li></ul><ul><ul><ul><li>CDRAM can prefetch data from DRAM into SRAM buffer </li></ul></ul></ul><ul><ul><ul><li>Subsequent accesses solely to SRAM </li></ul></ul></ul>
  16. 16. Flash memory <ul><li>Similar technology as EEPROM i.e. single transistor controlled by trapped charge </li></ul><ul><li>A single cell can be read but writing is on block basis and previous contents has to be removed </li></ul><ul><li>Greater density and a lower cost per bit, and consumes less power for operation </li></ul><ul><li>Used in MP3 players, Cell phones, digital cameras </li></ul>
  17. 17. DIMM Memory Modules and Slots
  18. 18. SIMM Memory Modules
  19. 19. Finally Memory Interleaving <ul><li>Main memory is structured as a collection of physically separate modules </li></ul><ul><li>Each having its own ABR and DBR </li></ul><ul><li>Memory access operation can be in more than one module at the same time </li></ul><ul><li>How the individual addresses are distributed over the modules, is the key? </li></ul><ul><li>Two common distributions are: </li></ul><ul><ul><li>Consecutive words in a module </li></ul></ul><ul><ul><li>Consecutive words in consecutive modules also called memory interleaving </li></ul></ul>