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  • For additional information, contact any of the following individuals: Dan Solarek Professor and Chairman [email_address] [email_address] Voice: 419-530-3377 Allen Rioux Director of Online Services [email_address] [email_address] Voice: 419-530-3377 To leave a message for any of these individuals call the department secretary at 419-530-3159. You may send a FAX to 419-530-3068 Richard Springman Director of Student Services [email_address] [email_address] Voice: 419-530-3276 Myrna Swanberg Academic Program Coordinator [email_address] [email_address] Voice: 419-530-3062
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    1. 1. CSET 4650 Field Programmable Logic Devices Dan Solarek Introduction to PLDs
    2. 2. Objectives <ul><li>Review of Digital Systems </li></ul><ul><li>History of PLDs </li></ul><ul><li>Types of PLDs </li></ul><ul><li>Terminology </li></ul>
    3. 3. Some Basics <ul><li>a combinational logic circuit is one where the next output depends only on the current input </li></ul>any number of inputs any number of outputs logic gates AND, OR, NOT (typically 7400 series SSI)
    4. 4. Some Basics <ul><li>a sequential logic circuit is one where the next output depends not only on the current input but also on the sequence of past inputs </li></ul>usually flip-flops SR, JK, D, T
    5. 5. Some Basics <ul><li>the design of a sequential logic circuit includes the design of a combinational logic circuit </li></ul>any number of inputs any number of outputs logic gates AND, OR, NOT (typically 7400 series SSI)
    6. 6. Purpose of this Course <ul><li>This course is about logic circuit implementation </li></ul>X 1 X 2 Q 1 Q 2 Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 x 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 x 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 ? function specification truth table Karnaugh Map circuit
    7. 7. Logic Circuit Implementation <ul><li>there are several options </li></ul>SSI Gates MSI ICs Memory
    8. 8. Logic Circuit Implementation <ul><li>there are several options </li></ul>U19-251641-02 PLA Programmable Devices
    9. 9. Electronic Components <ul><li>Common Resources </li></ul><ul><li>Configurable Logic Blocks (CLB) </li></ul><ul><ul><li>Memory Look-Up Table (LUT) </li></ul></ul><ul><ul><li>AND-OR planes </li></ul></ul><ul><ul><li>Simple gates </li></ul></ul><ul><li>Input / Output Blocks (IOB) </li></ul><ul><ul><li>Bidirectional, latches, inverters, pullup/pulldowns </li></ul></ul><ul><li>Interconnect or Routing </li></ul><ul><ul><li>Local, internal feedback, and global </li></ul></ul>Programmable Logic Devices (PLDs) Gate Arrays Cell-Based ICs Full Custom ICs SPLDs (PALs) FPGAs Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array ASIC = Application Specific IC Logic Standard Logic ASIC CPLDs
    10. 10. How Do You Make a “Programmable” Circuit? <ul><li>One time programmable </li></ul><ul><ul><li>Fuses (destroy internal links with current) </li></ul></ul><ul><ul><li>Anti-fuses (grow internal links) </li></ul></ul><ul><ul><li>PROM </li></ul></ul><ul><li>Reprogrammable </li></ul><ul><ul><li>EPROM </li></ul></ul><ul><ul><li>EEPROM </li></ul></ul><ul><ul><li>Flash </li></ul></ul><ul><ul><li>SRAM - volatile </li></ul></ul>} non-volatile
    11. 11. Programmable ROM (PROM) <ul><li>First ones had fusible links </li></ul><ul><li>High voltage would blow out links </li></ul><ul><li>Fast to program </li></ul><ul><li>Single use </li></ul>
    12. 12. UV EPROM <ul><li>Erasable PROM </li></ul><ul><li>Common technologies used UV light to erase complete device </li></ul><ul><ul><li>Took about 10 minutes </li></ul></ul><ul><li>Holds state as charge in very well insulated areas of the chip </li></ul><ul><li>Nonvolatile for several (10?) years </li></ul>
    13. 13. EEPROM <ul><li>Electrically Erasable PROM </li></ul><ul><li>Similar technology to UV EPROM </li></ul><ul><li>Erased in blocks by higher voltage </li></ul><ul><li>Programming slower than reading </li></ul><ul><li>Some called flash memory </li></ul><ul><ul><li>Digital cameras, MP3 players, BIOS </li></ul></ul><ul><ul><li>Limited life </li></ul></ul><ul><ul><li>Some support individual word write, some block </li></ul></ul><ul><ul><li>One on Xess board has 5 blocks </li></ul></ul><ul><ul><li>Has a boot block that is carefully protected </li></ul></ul>
    14. 14. Details of ROM <ul><li>Memory that is permanent </li></ul><ul><li>k address lines </li></ul><ul><li>2 k items </li></ul><ul><li>n bits </li></ul>a combinational logic circuit
    15. 15. Simple PLDs
    16. 16. Programmable Logic Device <ul><li>A programmable logic device or PLD is an electronic component used to build digital circuits. </li></ul><ul><li>Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. </li></ul><ul><li>Before the PLD can perform in a circuit it must be programmed. </li></ul>
    17. 17. Programmable Array Logic (PAL) <ul><li>The first programmable logic devices were produced by the Advanced Micro Devices (AMD) corporation. </li></ul><ul><li>The devices were called PALs, for programmable array logic. </li></ul><ul><li>The PLD business split from AMD under the name Vantis, and was acquired by Lattice Semiconductor in 1999. </li></ul>
    18. 18. Early PALs <ul><li>The programmable array contains logic gates, themselves fixed in function, with programmable interconnections between them. </li></ul><ul><li>The array has a number of inputs and outputs, and can create any Boolean function of a selection of the inputs at any of its outputs. </li></ul><ul><li>A single PAL can replace a circuit containing a large number, perhaps a few hundred, of fixed logic gates. </li></ul>
    19. 19. Early PALs <ul><li>In a PAL the logic gates are arranged as a sum-of-products array. </li></ul><ul><li>In Boolean terms, this means a number of AND gates whose outputs feed into a large OR gate that drives one output. </li></ul><ul><li>By selecting which inputs drive each AND gate, and which AND gates drive the OR gate, any Boolean function can be created. </li></ul>
    20. 20. Early PALs <ul><li>A PAL is programmed by fitting it into a machine called a PAL programmer. </li></ul><ul><li>PAL programmers are usually general-purpose machines that can program all types of PLDs from all manufacturers. </li></ul><ul><li>A PAL may be programmed only once. </li></ul>
    21. 21. Early PALs <ul><li>The PAL programmer must be supplied with a description of the PAL's desired configuration. </li></ul><ul><li>This is usually in the form of a computer text file with a standard format defined by the Joint Electron Device Engineering Council (JEDEC). </li></ul><ul><li>JEDEC files can be hand-typed by the design engineer or, more commonly, produced by a computer program similar to the language compilers used by software engineers. </li></ul>
    22. 22. Generic Array Logic (GAL) <ul><li>An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice Semiconductor Inc. </li></ul><ul><li>This device has the same logical properties as the PAL but can be erased and reprogrammed. </li></ul><ul><li>The GAL is very useful in the prototyping stage of a design, when any bugs in the logic can be corrected by reprogramming. </li></ul><ul><li>GALs are programmed and reprogrammed using a PAL programmer. </li></ul>
    23. 23. Programmable Electrically Erasable Logic (PEEL) <ul><li>A PEEL is a device similar to a GAL and was introduced by the Integrated Circuit Technology (ICT) corporation. </li></ul><ul><li>As the name implies, it differs from a GAL or PAL in that it is electrically erasable (reprogrammable) </li></ul>
    24. 24. Complex Programmable Logic Devices (CPLDs) <ul><li>Xilinx devices that are cheaper and have fewer gates than FPGAs </li></ul><ul><li>Meant for interfacing rather than heavy computation </li></ul><ul><li>Built-in flash memory </li></ul><ul><ul><li>Instead of FPGA, which needs external </li></ul></ul><ul><li>Xess bd. has XC9572XL part </li></ul><ul><ul><li>Approx $2-$7 in one’s qty. (vs. ~$15-20 for the Spartan2 on the board). Larger qty much lower. </li></ul></ul><ul><ul><li>1600 gates, 72 registers </li></ul></ul>
    25. 25. Complex PLDs <ul><li>PALs and GALs are available only in small sizes, equivalent to a few hundred logic gates. </li></ul><ul><li>For bigger logic circuits, complex PLDs or CPLDs can be used. </li></ul><ul><li>These contain the equivalent of several PALs linked by programmable interconnections, all in one integrated circuit. </li></ul><ul><li>CPLDs can replace thousands, or even hundreds of thousands, of logic gates. </li></ul>
    26. 26. Complex PLDs <ul><li>Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins. </li></ul><ul><li>A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer. </li></ul><ul><li>The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function. </li></ul>
    27. 27. Complex PLDs <ul><li>Each manufacturer has a proprietary name for its CPLD programming system. </li></ul><ul><li>For example, Lattice calls it &quot;in-system programming&quot;. </li></ul><ul><li>However, these proprietary systems are beginning to give way to a standard from the Joint Test Action Group (JTAG). </li></ul>
    28. 28. Field Programmable Logic Devices (FPGAs) <ul><li>While PALs were busy developing into GALs and CPLDs, a separate stream of development was happening. </li></ul><ul><li>This type of device is based on gate-array technology and is called the field-programmable gate array (FPGA). </li></ul>
    29. 29. Field Programmable Logic Devices (FPGAs) <ul><li>Gate arrays are non-programmable devices that can be manufactured more cheaply than other types of IC, because they contain a standard grid of logic gates whose interconnections are specified by the customer. </li></ul><ul><li>When a customer orders a new type of chip, the manufacturer does not have to design it from scratch, but can just take a standard gate array and modify it to the customer's requirement. </li></ul>
    30. 30. Field Programmable Logic Devices (FPGAs) <ul><li>FPGAs use a similar grid of logic gates, but the programming is done by the customer, not by the manufacturer. </li></ul><ul><li>The term &quot;field-programmable&quot; may be obscure to some, but the &quot;field&quot; is just an engineering term for the world outside the factory where customers live. </li></ul>
    31. 31. Field Programmable Logic Devices (FPGAs) <ul><li>FPGAs are usually programmed after being soldered down to the circuit board, in the same way as larger CPLDs. </li></ul><ul><li>In most larger FPGAs the configuration is volatile, and must be re-loaded into the device whenever power is applied or different functionality is required. </li></ul>
    32. 32. Field Programmable Logic Devices (FPGAs) <ul><li>FPGAs and CPLDs are often equally good choices for a particular task. </li></ul><ul><li>Sometimes the decision is more an economic one than a technical one, or may depend on the engineer's personal preference and history. </li></ul>
    33. 33. *note: Xilinx Virtex-II Pro XC2VP100 (9/16/2003) PLD Device Density and VLSI Technology 1B 0.07µ 2004 ? 430M 75M 23M 12M 3.5M Transistor Count 100K LC* 8Mb RAM 400 18X18 multipliers 1 M 250K 100K 25K Gate Count 0.13 µ 0.18 µ 0.25 µ 0.35 µ 0.6µ Technology 2003 2000 1997 1996 1995 Year
    34. 34. How PLDs Remember Their Configuration <ul><li>A PLD is a combination of a logic device and a memory device. </li></ul><ul><li>The memory is used to store the pattern that was given to the chip during programming. </li></ul><ul><li>Most of the methods for storing data in an integrated circuit have been adapted for use in PLDs. </li></ul>
    35. 35. How PLDs Remember Their Configuration <ul><li>The methods for storing data in an integrated circuit include: </li></ul><ul><ul><li>silicon antifuses </li></ul></ul><ul><ul><li>static RAM (SRAM) </li></ul></ul><ul><ul><li>flash memory </li></ul></ul><ul><ul><li>EPROM cells </li></ul></ul>
    36. 36. How PLDs Remember Their Configuration - Antifuses <ul><li>Silicon antifuses are the storage elements used in the PAL, the first type of PLD. </li></ul><ul><li>These are connections that are made by applying a voltage across a modified area of silicon inside the chip. </li></ul><ul><li>They are called antifuses because they work in the opposite way to normal fuses, which begin life as connections until they are broken by an electric current. </li></ul>
    37. 37. How PLDs Remember Their Configuration - SRAM <ul><li>SRAM, or static RAM, is a volatile type of memory, meaning that its contents are lost each time the power is switched off. </li></ul><ul><li>SRAM-based PLDs therefore have to be programmed every time the circuit is switched on. </li></ul><ul><li>This is usually done automatically by another part of the circuit. </li></ul>
    38. 38. How PLDs Remember Their Configuration - Flash <ul><li>Flash memory is non-volatile, retaining its contents even when the power is switched off. </li></ul><ul><li>It can be erased and reprogrammed as required. </li></ul><ul><li>This fact makes flash memory useful for PLD memory. </li></ul>
    39. 39. How PLDs Remember Their Configuration - EPROM <ul><li>An EPROM cell is a MOS (metal-oxide-semiconductor) transistor that can be switched on by trapping an electric charge permanently on its gate electrode. </li></ul><ul><li>This is done by a PAL programmer. </li></ul><ul><li>The charge remains for many years and can only be removed by exposing the chip to strong ultraviolet light in a device called an EPROM eraser. </li></ul>
    40. 40. PLD Programming Languages <ul><li>PLD programming languages </li></ul><ul><ul><li>PALASM </li></ul></ul><ul><ul><li>ABEL </li></ul></ul><ul><ul><li>CUPL </li></ul></ul>
    41. 41. Hardware Description Languages <ul><li>The languages used as source code for logic compilers are called hardware description languages, or HDLs. </li></ul><ul><li>Examples of HDLS include: </li></ul><ul><ul><li>VHDL </li></ul></ul><ul><ul><li>Verilog HDL </li></ul></ul><ul><ul><li>AHDL </li></ul></ul>
    42. 42. Programmable Logic Solutions <ul><li>No high development cost barriers </li></ul><ul><li>Recovered time for authoring and innovating </li></ul><ul><ul><li>SW improvements reduce design iterations </li></ul></ul><ul><li>No lengthy prototyping cycle </li></ul><ul><li>Ability to remotely upgrade any networked system </li></ul><ul><li>Ultimate flexibility to manage rapid change </li></ul>