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  1. 1. ITRS Test ITWG December 2002
  2. 2. Test ITWG Membership <ul><li>Industry </li></ul><ul><ul><li>Agere </li></ul></ul><ul><ul><li>IBM </li></ul></ul><ul><ul><li>Infineon </li></ul></ul><ul><ul><li>Intel </li></ul></ul><ul><ul><li>Matsushita </li></ul></ul><ul><ul><li>Motorola </li></ul></ul><ul><ul><li>NEC </li></ul></ul><ul><ul><li>Philips </li></ul></ul><ul><ul><li>ST Microelectronics </li></ul></ul><ul><ul><li>Texas Instruments </li></ul></ul><ul><li>Suppliers </li></ul><ul><ul><li>Advantest </li></ul></ul><ul><ul><li>Agilent </li></ul></ul><ul><ul><li>Inovys </li></ul></ul><ul><ul><li>Schlumberger </li></ul></ul><ul><ul><li>Synopsys </li></ul></ul><ul><ul><li>Teradyne </li></ul></ul>Participation from Taiwan and Korea regions needed!
  3. 3. 2002 ITRS Test Chapter Update <ul><li>Trends described in 2001 have held true </li></ul><ul><ul><li>High speed interfaces are appearing in a broad range of applications in many market segments </li></ul></ul><ul><ul><li>SOC and SIP dominate new designs </li></ul></ul><ul><ul><li>Low cost, targeted test platforms emerging </li></ul></ul>The 2002 update will bring only minor adjustments to the trends defined in 2001
  4. 4. 2003 ITRS Test Chapter <ul><li>Increased focus on key challenges and potential solutions will be the primary change in 2003! </li></ul><ul><li>New Additions </li></ul><ul><ul><li>Reliability Methods </li></ul></ul><ul><ul><li>Handler and Prober Equipment </li></ul></ul><ul><ul><li>Sockets and Probecards </li></ul></ul><ul><li>Updates </li></ul><ul><ul><li>High Frequency Serial Communications </li></ul></ul><ul><ul><li>High Performance ASIC </li></ul></ul><ul><ul><li>High Performance Microprocessor </li></ul></ul><ul><ul><li>Low-end Microcontroller </li></ul></ul><ul><ul><li>Mixed Signal and Wireless </li></ul></ul><ul><ul><li>DFT Tester </li></ul></ul><ul><ul><li>Embedded and Commodity DRAM and Flash </li></ul></ul>
  5. 5. 2001 Key Challenges <ul><li>High Speed Device Interfaces </li></ul><ul><li>Highly Integrated Designs & SOCs </li></ul><ul><li>Reliability Screens </li></ul><ul><li>Manufacturing Test Cost Reduction </li></ul><ul><li>Test Software Standards </li></ul><ul><li>Modeling and Simulation </li></ul>
  6. 6. Demand for Bandwidth <ul><li>Penetration of high speed interfaces into new designs is increasing dramatically </li></ul><ul><li>Learning rate for ATE solutions lags leading edge device technology </li></ul><ul><li>Test and DFT methods must be developed to enable development and production test of these products </li></ul>
  7. 7. High Integration Devices & SOC <ul><li>Customer requirements for form factor and power consumption are driving a significant increase in design integration levels </li></ul><ul><ul><li>Test complexity will increase dramatically with the combination of different classes of circuits on single die or within a single package </li></ul></ul><ul><ul><li>Disciplined, structured DFT is a requirement to reduce test complexity </li></ul></ul><ul><li>New test methods and equipment architectures must be developed </li></ul><ul><ul><li>Enable a merge of logic and analog test capability with the throughput of high density memory test equipment </li></ul></ul>
  8. 8. Reliability Screens Run Out of Gas <ul><li>Critical need for development of new techniques for acceleration of latent defects </li></ul><ul><ul><li>Burn-in methods limited by thermal runaway </li></ul></ul><ul><ul><li>Lowered use voltages limits voltage stress opportunity </li></ul></ul><ul><ul><li>Difficulty of determining Iddq signal versus “normal” leakage current noise </li></ul></ul><ul><li>New materials </li></ul><ul><ul><li>Rate of introduction increasing: Cu, low k, high k, SiGe </li></ul></ul><ul><ul><li>Increasing mechanical sensitivities </li></ul></ul><ul><li>Rapid growth of Fabless business model </li></ul><ul><ul><li>Organizational and corporate boundaries - lack of clear ownership of reliability in distributed business models </li></ul></ul>
  9. 9. Scaling Component Test Cost <ul><li>Recent steps have enabled test cost to begin to scale across technology nodes </li></ul><ul><ul><li>Equipment reuse across nodes </li></ul></ul><ul><ul><li>Increasing test throughput </li></ul></ul><ul><li>Challenge remains in most segments, especially high speed and high integration products </li></ul>
  10. 10. Dismantling the Red Brick Walls <ul><li>Design For Test enabling has begun to remove many of the roadblocks that appeared in the 1997 and 1999 roadmaps </li></ul><ul><ul><li>Test is becoming integrated with the design process </li></ul></ul><ul><ul><li>Improvements demonstrated in capability and cost </li></ul></ul><ul><li>Continued research is needed into new and existing digital logic fault models toward identification of true process defects </li></ul><ul><li>Development of Analog DFT methods must advance </li></ul><ul><ul><li>Formalization of analog techniques and development of fault models </li></ul></ul>
  11. 11. Test Software Standards Focus <ul><li>Standards for test equipment interface & communication are needed to decrease equipment factory integration time </li></ul><ul><ul><li>Improve equipment interoperability to reduce factory systems integration time </li></ul></ul><ul><ul><li>e.g, built into 300mm equipment specifications </li></ul></ul><ul><li>Standards for ATE software and test program generation are needed to decrease test development effort and improve time to market </li></ul><ul><ul><li>Lower the barrier for selecting the optimal equipment </li></ul></ul><ul><li>Increased focus for standards development and adoption of existing standards </li></ul>
  12. 12. How can we improve manageability of the divergence between validation and manufacturing equipment? What happens when high speed serial interfaces become buses? Can ATE instruments catch up and keep up with high speed serial performance trends? Will market dynamics justify development of next generation functional test capabilities? Can DFT and BIST mitigate the mixed signal tester capability treadmill? What other opportunities exist? How can we make test of complex SOC designs more cost effective? Will increasing test data volume lead to increased focus on Logic BIST architectures? What are the other solutions? Can DFT mitigate analog test cost as does in the digital domain? What is the cost and capability optimal SOC test approach?
  13. 13. Test Implications of IP Design <ul><li>Test Strategy and Integration </li></ul><ul><ul><li>DFT for IP Core Based Design </li></ul></ul><ul><ul><li>Higher Level DFT </li></ul></ul><ul><li>Standardization </li></ul>IP Core Based Design Logic MCU Memory Control DSP Analog BISR/BIRA Path Delay BOST Test Strategy Analog Isolation Scan+ATPG IP Core Isolation BIST
  14. 14. Automated DFT Insertion <ul><li>Automation of test control integration and test scheduling </li></ul><ul><ul><li>Insert test wrapper and test control circuits </li></ul></ul>SoC DFT IP Core Test Data Chip-Level Test Data Test Wrapper DFT Test Controller Test Wrapper Insertion Test Data Conversion Configuration of Chip-Level Test Controller and Test Access Mechanism
  15. 15. Preliminary Roadmap for Handlers Memory 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016 Parallel Testing Index Time Throughput Temp. Control Temp. Accuracy Foot Print 32 to 64 64 to 128 3 to 5 2 to 5 2 to 4 6 to 8 8 to 10 8 to 12 -55 to 100 +/- 3 +/- 2 +/- 2 +/- 1.5 1 to 1.3 1.3 to 1.5 per head Sec. thousands / hour degree degree ratio *2 *1 Note Logic 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016 4 8 0.3 to 0.4 to 0.25 4 to 6 8 to 12 12 to 20 Room Temp. to 125 +/- 3 +/- 2 +/- 2 +/- 1 1 1.2 *2 *1 Note 16 9 to14 1.4 Parallel Testing Index Time Throughput Temp. Control Temp. Accuracy Foot Print per head Sec. thousands / hour degree degree ratio *1 Though 128 become number of parallel testing after 2005 years, it is difficult to keep the temperature accuracy that 64 are the same as the number of parallel testing with memory handler.Therefore, it becomes yellow. Though 8 become number of parallel testing after 2004 years, it is difficult to keep the temperature accuracy that 4 are the same as the number of parallel testing with logic handler. Therefore, it becomes yellow. *2 It is expressed by the index number when 32 of parallel testing in 2001 is made 1. (Therefore, it becomes 1.3 by 64 of parallel testing in 2001.).
  16. 16. Preliminary Roadmap for Handlers Device flow Tray flow Tray Loader UnLoader JEDEC Temp. control Achieving the same temperature accuracy in handlers with 128 devices handled in parallel, as handlers with 64 will be very difficult and challenging. Parallel testing Memory 64 to 128 (2005) Foot print Considering the size of the handler needed to access the test floor, the test floor layout, and other transportation restrictions, the handler width should not exceed 1.8 m. Logic 4 to 8 (2004) to 16 (2010) Make the handling faster. Make the conveyance distance shorter. More accurate positioning will make the handling time shorter. Test head The test head size is becoming larger year by year. Socket Device Handler is required to handle diversifying various kinds of packages. Index time Test frequency Keep an electrical stable contact
  17. 17. Preliminary Roadmap for Sockets Molded board type 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016 Inductance Contact stroke Contact pressure Contact resistance Guarantee marginal value 3 to 8 2 to 8 0.3 to 0.5 20 to 40 30 nH mm g mOhm durability 20 to 40 10000 Spring probe type 2 to 8 1 to 8 0.3 to 0.5 20 to 40 150 10000 New generation type 1 to 8 0.1 to 0.3 30 13 to 28 10000 0.3 13 to 40 13 to 28 100 10000 10000 Inductance Contact stroke Contact pressure Contact resistance nH mm g mOhm durability Inductance Contact stroke Contact pressure Contact resistance nH mm g mOhm durability Note The performance has ripened and there is no big change. Contact pressure is difficult at lead free correspondence. Note The limit over the diameter reduction of a terminal is in sight. Note If opposite cost is taken into consideration, at a present stage, it is not practical. 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016 Guarantee marginal value Guarantee marginal value * Guarantee marginal value : The number of times of a use limit which an offer company guarantees.
  18. 18. Preliminary Roadmap for Sockets A trend of Socket Leaf spring type Spring probe system Surface mount type of stamping Surface mount of stamping contact pin with rubber component Particle inter-connect Barrel less type of spring probe pin One side actuating type of spring probe pin Leaf spring type Film type Rubber type Micro-spring Peripheral Area Array Need to develop novel contactor such as zero-force architecture for ultra high pin counts (narrow pitch) and high speed device testing. ? ?
  19. 19. Modeling and Simulation Difficulty of test development for design & Virtual tester tech. Virtual tester technology Correct products? Correct test program? Correct test equipment? Difficult triangular ・ ・ ・ ・ ・ ・ wrong wiring ・ miss relay control point ・ Ground noise ・ wrong parts ・ probe card (inductance) ・ reflection(missmatched Z) ・ ・ ・ ・ ・ ・ imperfect circuit understanding ・ not fix test spec. ・ complex conditions of timing etc ・・・・ Virtual test operation De fac’to program description Test Board verification tech. ・ Tester resource problems (timing,pattern length, etc.) ・ Tester limitation(clump) ・ Wait time ・ Different tester
  20. 20. Modeling and Simulation Socket / Probe Test board Tester Formation of many pins Formation of a special package A large number are taken. Workability, Speed Conversion Machine figure presentation, target electrical property presentation Equivalent length wiring, target transmission impedance Electric circuit parameter extraction (Electro magnetic analysis) Optimize wiring , Adjust processing (Board analysis)          Concentration constant (Comparator capacity, driver impedance) It is overly high-speed testing. High frequency Transition line consideration Distributed Model, Tester Mode (Tester transmission way analysis technology) Test - Board DUT- Tester transmission DR CP x Socket Small board Test board Conversion board Tester mother board Tester pin electronics Socket/ Probe Tester Subject: socket / probe, a test board, and a tester Even if each shows information, the whole test board verification is difficult. Device Output voltage, current regulation (Voh,Vol,Ioh,Iol Device improvement in the speed, customer situation consideration    (RAMBUS, cellular phone) output SPICE and IBS model (Customer board design consideration) New business The necessity for a model Test board verification technology High-speed tester (125MHz) test mode waveform analysis Fig 2   T6672 Tester Ringing Countermeasure Method L/ R Circuit Diode   Clamp   Circuit I-LOAD   Circuit CP 1V 6 V CP 24mA -24mA 3V tr=2.0ns/tf=2.4ns tr=1.3ns/tf=1.8ns tr=2.3ns/tf=12.8ns R S R L ∽ 25Ω 350mH Block ring