Perifericos Embebidos en el AT91RM9200


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  • This training module provides an overview of the advanced peripheral functions available on the AT91RM9200. It’s important to emphasis the fact that ATMEL is not just another ARM based microcontroller supplier. The core is one thing but the richness and complexity of associated peripheral will make whole architecture a real solution for embedded applications.
  • The AT91RM9200 embedds an external Bus Interface called EBI designed to ensure the successful data transfert between several external devices and the embedded memory controller. The EBI integrates three external memory controllers, the static memory controller, the sdram controller and the burst flash controller. The EBI also supports the compact flash and the smartmedia protocols via integrated circuitry that greatly reduces the requirements for external components. The EBI handles data transferts with up to eight esternal devices. Data transfert are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to 8 chip select lines and several control pins that are generally multiplexed between the different external memory controllers.
  • This block diagram shows the organisation of the External Bus Interface.
  • The Static Memory Controller (SMC) generates the signals that control the access to external static memory or peripheral devices. The SMC is fully programmable and can address up to 512MB. It has 8 chip selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8 to 16-bit external devices. The SMC can be configured to work with an external LCD controller, the NCS is shortened by 1/2/3 clock cycles at the leading and traiting edges, providing positive address setup and hold. It also provides an external wait request capability.
  • The SDRAM Controller extends the memory capabilities by providing the interface to an external 16-bit or 32-bit SDRAM device. The SDRAMC can address up to 256MB. It supports byte, half word and word accesses.
  • The Burst Flash Controller provides an interface for external 16-bit burst Flash devices and handles an address space of 256MB. It supports byte, half word and word aligned accesses and can access up to 32MB of burst Flash devices. The BFC also supports data bus and address bus multiplexing.
  • The Power Management Controller (PMC) generates all the clocks of a system thanks to the integration of two oscillators and two PLLs and optimizes the power consumption of the whole system. The PMC provides the Processor clock (PCK), the Master clock (MCK), the USB clocks (UHPCK and UDPCK) required for the USB Host Port and the USB Device Port.
  • The PMC supports four operating modes, normal, idle, slow clock and standby and offers different power consumption levels. In normal mode, the arm processor clock is enabled and peripheral clocks are enabled depending on application requirements. In idle mode, the arm processor is disabled and waiting for the next interrupt, peripherals are enabled, PDC transfers are still possible. The slow clock mode is similar to the normal mode, but the main oscillator and PLLs are switched off to save power and the processor and peripherals run in slow clock mode. The standby mode is a combination of slow clock mode and idle mode. It enables the processor to respond quickly to a wake up event by keeping power consumption very low.
  • This Block Diagram shows the organization of the Power Management Controller.
  • The Advanced Interrupt Controller (AIC) drives the nFIQ (Fast Interrupt) and the nIRQ (standard Interrupt) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The AIC provides handling of up to thirty two interrupt sources. It is designed to substantially reduce the software and real time overhead in handling internal and external interrupts. Internal interrupts sources can be programmed to be level sensitive or edge triggered. External interrupts sources can be programmed to be positive edge or negative edge triggered or high level or low level sensitive.
  • An eight-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occuring on the interrupt sources 1 to 31. Each interrupt source has a programmable priority level of 7 to 0, level 7 is the highest priority level.
  • Automatic Vectoring offers a way to branch in one single instruction to the handler correponding to the current interrupt, each interrupt source handler address are stored in the source vector register 1 to 31.
  • The Fast forcing feature of the AIC provides redirection of any normal interrupt source on the fast interrupt controller. The AIC features a general interrupt mask bit to prevent interrupts from reading the processor.
  • The priority controller utilizes interrupt nesting in order for the highest priority interrupt to be handled during the service of lower priority interrupts.
  • The Peripheral Data Controller (PDC) transfers data between on-chip serial peripherals such as the USART, SSC, SPI, MCI and the on and off-chip memories. Using the PDC avoids processor intervention and removes the processor interrupt handling overhead. This significantly reduces the number of clock cycles required for a data transfer and improvesthe performance of the microcontroller.
  • The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each USART, SSC and SPI.
  • The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains a 32-bit memory pointer register, a 16-bit transfer counter register, a 32-bit register for next memory pointer and a 16-bit register for next transfer count.
  • The Multimedia Card Interface (MCI) supports the Multimedia Card specification V2.2 and the SD Memory Card specification V1.0. The MCI operates at a rate of up to master clock divided by 2 abd supports interfacing of up to 16 slots. The MCI is compatible with the PDC channels. Each slot may be used to interface with a MMC bus or with a SD Memory card.
  • The Multimedia Card communication is based on a 7-pin interface with clock, command, one data and three power lines.
  • The SD Memory card communication is based on a 9-pin interface with clock, command, four data and three power lines.
  • The USART provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The Usart features three test modes, remote loopback, local loopback and automatic echo. Multi Drop communications are also supported through address bit handling in reception and transmission. The USART supports specific operating modes providing interfaces on RS485 busses, with ISO7816 T=0 or T=1 smart card slots, Infrared transceivers and connection to modem ports.
  • The USART features a hardware handshaking out of band flow control. The RTS and CTS pins are used to connect with the remote devices as shown in this figure. The ISO7816 compatible operating mode permits interfacing with smart cards and security access modules (SAM) communicating through an ISO7816 link. The TXD line becomes bidirectional and the baud rate generator feeds the ISO7816 clock on the SCK pin.
  • The USART features an IrDA mode supplying half-duplex poitn to point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceives as shown in this figure. The RS485 mode allows to enable line driver control. Typical connection of the USART to a RS485 bus is shown in this figure.
  • The Serial Peripheral Interface (SPI) is a synchronous serial data link that provides communication with external devices in Master or Slave mode. The main features are 4 chip selects with external decoder, support up to 15 peripherals, 8 to 16-bit programmable data length, connection to PDC channels capabilities to optimize data transfert.
  • This figure shows an example of SPI Bus.
  • The Two Wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock and one data line whith speeds of up to 400kbit/s. It can be used with any Atmel two-wire serial EEPROM.
  • The System Timer module integrates three different free-running timers: a periodic interval timer (PIT) that sets the time base for an OS, a watchdog timer with system reset capabilities in case of software deadlock, a real time timer counting elapsed seconds. These timers count using the slow clock, typically 32.768KHz.
  • The Timer/Counter includes three identical 16-bit timer counter channels. Each channel can be independently programmable to perform a wide range of functions including frequency measurement, event counting, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi purpose I/O signals which can be configured by the user.
  • The Real Time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time of day clock with alarm and a two hundred year gregorian calendar, complemented by a programmable periodic interrupt. The time and calendar values are coded in binary code decimel (BCD) format.
  • The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer PHY and the logical link layer. It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3 data frame format. The Ethernet MAC can transfer data in Media Independent Interface (MII) or reduced Media Independent Interface (RMII) modes.
  • The Serial Synchronous Controller (SSC) provides asynchronous communication link with external devices. It supports many serial synchronous communication protocols, generally used in audio and telecom applications such as I²S, short frame sync, ... The SSC contains an independent receiver and transmitter and a common clock divider. Each interface with three signals, data, clock and frame synch.
  • Perifericos Embebidos en el AT91RM9200

    1. 1. AT91RM9200 Embedded Peripherals
    2. 2. External Bus Interface <ul><li>Integrates three external memory controllers </li></ul><ul><ul><li>Static Memory Controller, SDRAM Controller and Burst Flash Controller </li></ul></ul><ul><li>Additional logic for SmartMedia and CompactFlash support </li></ul><ul><li>Optimized external bus </li></ul><ul><ul><li>16 or 32-bit data bus </li></ul></ul><ul><ul><li>Up to 26-bit address bus, up to 64M Bytes addressable </li></ul></ul><ul><ul><li>Up to 8 chip selects </li></ul></ul><ul><ul><li>Optimized pin multiplexing to reduce latencies on external memories </li></ul></ul>
    3. 3. External Bus Interface <ul><li>Block Diagram </li></ul>
    4. 4. External Bus Interface <ul><li>Static Memory Controller </li></ul><ul><ul><li>External memory mapping, 512M Bytes address space </li></ul></ul><ul><ul><li>Up to 8 chip select lines </li></ul></ul><ul><ul><li>8 or 16-bit data bus </li></ul></ul><ul><ul><li>Byte write or Byte select lines </li></ul></ul><ul><ul><li>Remap of Boot Memory </li></ul></ul><ul><ul><li>Programmable wait state generation, Data float time, Setup time Read/Write, Hold time Read/Write </li></ul></ul><ul><ul><li>Compliant with LCD Module </li></ul></ul><ul><ul><li>External Wait Request </li></ul></ul>
    5. 5. External Bus Interface <ul><li>SDRAM Memory Controller </li></ul><ul><ul><li>External memory mapping, 256M Bytes address space </li></ul></ul><ul><ul><li>Supports an SDRAM with two or four internal banks </li></ul></ul><ul><ul><li>Supports an SDRAM with 16 or 32-bit data path </li></ul></ul><ul><ul><li>Automatic refresh operation, refresh rate is programmable </li></ul></ul><ul><ul><li>Supports self-refresh and low-power modes </li></ul></ul><ul><ul><li>Read or Write burst length of one location </li></ul></ul><ul><ul><li>Word, Half-word, Byte access </li></ul></ul><ul><ul><li>Multibank Ping-pong access </li></ul></ul><ul><ul><li>SDRAM power-up initialization by software </li></ul></ul><ul><ul><li>Refresh error interrupt </li></ul></ul>
    6. 6. External Bus Interface <ul><li>Burst Flash Controller </li></ul><ul><ul><li>16-bit data bus </li></ul></ul><ul><ul><li>Asynchronous or Burst mode read Byte, Half-word or Word accesses </li></ul></ul><ul><ul><li>Asynchronous mode Half-word write accesses </li></ul></ul><ul><ul><li>Programmable data access time </li></ul></ul><ul><ul><li>Programmable latency after output enable </li></ul></ul><ul><ul><li>Programmable Burst Flash clock rate </li></ul></ul><ul><ul><li>Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled </li></ul></ul><ul><ul><li>Multiplexed or Separate address and data buses </li></ul></ul>
    7. 7. External Bus Interface <ul><li>Compact Flash </li></ul><ul><ul><li>I/O mode : used for I/O peripherals like modems </li></ul></ul><ul><ul><li>Attribute memory mode : (0 -> 1FF) contains the card ID, manufacturer ID … </li></ul></ul><ul><ul><li>Common memory mode : allows to store data in memory </li></ul></ul><ul><ul><li>True IDE mode is not supported </li></ul></ul>
    8. 8. Power Management Controller <ul><li>PMC embeds and controls </li></ul><ul><ul><li>One main oscillator providing a frequency range [3 : 20] MHz </li></ul></ul><ul><ul><li>One slow clock oscillator (32768 Hz) </li></ul></ul><ul><ul><li>Two phase locked loops and dividers </li></ul></ul><ul><ul><li>Clock prescalers </li></ul></ul><ul><li>PMC provides clocks to the whole system </li></ul><ul><ul><li>Processor clock PCK : typically MCK but switched off when entering idle mode. </li></ul></ul><ul><ul><li>Master clock MCK, it is available to the modules running permanently </li></ul></ul><ul><ul><li>USB clocks UHPCK and UDPCK at 48MHz </li></ul></ul>
    9. 9. Power Management Controller <ul><li>Four operating modes </li></ul><ul><ul><li>Normal : processor and peripheral clocks are enabled </li></ul></ul><ul><ul><li>Idle : processor clock is disabled, waiting for interrupt, Peripheral clocks are enabled </li></ul></ul><ul><ul><li>Slow : processor and peripherals run at slow clock </li></ul></ul><ul><ul><li>Standby : combination of slow clock mode and idle mode. </li></ul></ul>
    10. 10. Power Management Controller <ul><li>Block Diagram </li></ul>
    11. 11. Advanced Interrupt Controller <ul><li>AIC controls the interrupt lines of an ARM processor </li></ul><ul><li>Thirty-two individually maskable and vectored interrupt sources </li></ul><ul><ul><li>Source 0 is reserved for the fast interrupt input </li></ul></ul><ul><ul><li>Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU …) </li></ul></ul><ul><ul><li>Sources 2 to 31 control up to thirty embedded peripheral interrupts or external interrupts. </li></ul></ul><ul><ul><li>Programmable Edge-triggered or Level-sensitive internal sources </li></ul></ul><ul><ul><li>Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive external sources </li></ul></ul><ul><ul><li>AIC enables/disables independently the thirty-two sources </li></ul></ul>
    12. 12. Advanced Interrupt Controller <ul><li>Eight-level priority controller </li></ul><ul><ul><li>Handles priority of the interrupt sources 1 to 31, the fast interrupt logic of the AIC has no priority controller </li></ul></ul><ul><ul><li>Higher priority interrupts can be served during service of lower priority interrupt </li></ul></ul>
    13. 13. Advanced Interrupt Controller <ul><li>Vectoring </li></ul><ul><ul><li>One 32-bit vector register per interrupt source, fast interrupt included </li></ul></ul><ul><ul><li>Interrupt vector register reads the corresponding current interrupt vector (handler address) </li></ul></ul><ul><ul><li>Branch in one single instruction to the right handler </li></ul></ul>
    14. 14. Advanced Interrupt Controller <ul><li>Fast forcing </li></ul><ul><ul><li>Redirects any normal interrupt source on the fast interrupt of the processor </li></ul></ul><ul><ul><li>Unlike IRQs and FIQs, fast forced interrupts aren’t cleared automatically </li></ul></ul><ul><li>General interrupt mask </li></ul><ul><ul><li>Prevents interrupts from reaching the processor </li></ul></ul><ul><ul><li>Processor can still be waken up even if the mask is set up </li></ul></ul><ul><ul><li>Provides processor synchronization on events without having to handle an interrupt </li></ul></ul>
    15. 15. Advanced Interrupt Controller <ul><li>Interrupt nesting </li></ul><ul><ul><li>Handles a high priority interrupt during the service of a lower priority interrupt </li></ul></ul><ul><ul><li>Current priority interrupt is pushed in an 8-level wide, embedded hardware stack </li></ul></ul><ul><li>Protect mode </li></ul><ul><ul><li>Allows to read the interrupt vector register without performing the associated automatic operations : stacking and clearing </li></ul></ul><ul><ul><li>This is necessary when working with debug </li></ul></ul><ul><ul><li>Interrupt stacking is performed by writing to the interrupt vector register </li></ul></ul>
    16. 16. Advanced Interrupt Controller <ul><li>Spurious interrupt </li></ul><ul><ul><li>Spurious vector is returned when the assertion of an interrupt does no longer exists when the IVR is read </li></ul></ul><ul><li>Application Block Diagram </li></ul>
    17. 17. Peripheral Data Controller <ul><li>PDC transfers data between on-chip serial peripherals and on- and off-chip memories. </li></ul><ul><ul><li>On-chip serial peripherals UART, USART, SSC, SPI, MCI </li></ul></ul><ul><li>Using PDC avoids processor intervention and removes interrupt-handling overhead </li></ul>
    18. 18. Peripheral Data Controller <ul><li>Two PDC Channels for Each peripheral </li></ul><ul><ul><li>Receive Channel </li></ul></ul><ul><ul><ul><li>Trigger = RXRDY </li></ul></ul></ul><ul><ul><ul><li>End of Transfer = ENDRX </li></ul></ul></ul><ul><ul><ul><li>Rx Buffer Full = RXBUFF </li></ul></ul></ul><ul><ul><li>Transmit Channel </li></ul></ul><ul><ul><ul><li>Trigger = TXRDY </li></ul></ul></ul><ul><ul><ul><li>End of Transfer = ENDTX </li></ul></ul></ul><ul><ul><ul><li>Tx Buffer Empty = TXBUFE </li></ul></ul></ul>PDC Receive Channel USART Trigger Status PDC Transmit Channel Triger Status Size = Byte Size = Byte
    19. 19. Peripheral Data Controller <ul><li>A PCD channel’s user interface is integrated in the memory space of each peripheral </li></ul><ul><ul><li>A 32-bit memory pointer register </li></ul></ul><ul><ul><li>A 16-bit transfer count register </li></ul></ul><ul><ul><li>A 32-bit register for next memory pointer </li></ul></ul><ul><ul><li>A 16-bit register for next transfer count </li></ul></ul>Tx Pointer Tx Counter US_TPR US_T N CR /TCR Tx Next Pointer US_T N PR Tx Next Counter R x Pointer R x Counter US_ R PR US_ RN CR /RCR R x Next Pointer US_ RN PR R x Next Counter
    20. 20. Multimedia Card Interface <ul><li>Supports MultiMediaCard specification version 2.2 </li></ul><ul><li>Supports SD Memory Card specification version 1.0 </li></ul><ul><li>MCI operates at a rate of up to master clock divided by 2 </li></ul><ul><li>Supports PDC connection </li></ul><ul><li>Embedded power management to slow down clock when the bus is inactive </li></ul><ul><li>Supports up to sixteen slots (through multiplexing) </li></ul><ul><ul><li>One slot for one MultiMediaCard Bus (up to 30 cards) or one SD Memory Card </li></ul></ul><ul><li>Support for stream, block and multi-block data read and write </li></ul>
    21. 21. <ul><li>MultiMediaCard Bus </li></ul><ul><ul><li>The MultiMediaCard communication is based on a 7-pin interface (clock, command, one data and three power lines). </li></ul></ul>Multimedia Card Interface
    22. 22. Multimedia Card Interface <ul><li>SD Memory Card Bus </li></ul><ul><ul><li>The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines). </li></ul></ul>
    23. 23. <ul><li>Features </li></ul><ul><ul><li>Programmable Baud Rate Generator </li></ul></ul><ul><ul><li>Parity, Framing and Overrun Error Detection </li></ul></ul><ul><ul><li>Line Break Generation and Detection </li></ul></ul><ul><ul><li>Automatic Echo, Local Loopback and Remote Loopback Channel Modes </li></ul></ul><ul><ul><li>Multi-drop Mode: Address Detection and Generation </li></ul></ul><ul><ul><li>Interrupt Generation </li></ul></ul><ul><ul><li>5, 6, 7, 8 and 9-bit Character Length </li></ul></ul><ul><ul><li>Protocol ISO7816 T=0 and T=1 </li></ul></ul><ul><ul><li>Modem, Handshaking (Hardware and Software) and RS485 Signals </li></ul></ul><ul><ul><li>Infrared Data Association (IrDA) 115.2 Kbps </li></ul></ul><ul><ul><li>Two Dedicated Peripheral Data Controller Channels </li></ul></ul>USART
    24. 24. <ul><li>Hardware Handshaking </li></ul><ul><li>ISO7816 Mode </li></ul>USART
    25. 25. <ul><li>IrDA Mode </li></ul><ul><li>RS485 Mode </li></ul>USART
    26. 26. <ul><li>Features </li></ul><ul><ul><li>Serial Interface between CPU and External Peripherals </li></ul></ul><ul><ul><li>Master or Slave Mode </li></ul></ul><ul><ul><li>Full duplex 3 wires synchronous transfer </li></ul></ul><ul><ul><ul><li>MISO: Master In Slave Out </li></ul></ul></ul><ul><ul><ul><li>MOSI: Master Out Slave In </li></ul></ul></ul><ul><ul><ul><li>SPCK: SPI Clock </li></ul></ul></ul><ul><ul><li>Maximum SPI baud rate clock: MCK/4 </li></ul></ul><ul><ul><li>4 External Slave chip selects </li></ul></ul><ul><ul><li>8 to 16-bit Programmable Data Length </li></ul></ul><ul><ul><li>Mode Fault Detection in Master Mode </li></ul></ul><ul><ul><li>2 Dedicated PDC Channels </li></ul></ul>Serial Peripheral Interface
    27. 27. <ul><li>Bus </li></ul>Serial Peripheral Interface
    28. 28. <ul><li>Features </li></ul><ul><ul><li>Master Mode </li></ul></ul><ul><ul><li>Compatible with Standard Two-wire Serial Memory </li></ul></ul><ul><ul><li>One, Two or Three Bytes for Slave Address </li></ul></ul><ul><ul><li>Sequential Read/write Operations </li></ul></ul>Two Wire Interface
    29. 29. <ul><li>Bus </li></ul>Two Wire Interface
    30. 30. <ul><li>Features </li></ul><ul><ul><li>One Period Interval Timer (PIT) </li></ul></ul><ul><ul><ul><li>16-bit programmable counter </li></ul></ul></ul><ul><ul><ul><li>periodic interrupt, useful for OS </li></ul></ul></ul><ul><ul><li>One Watchdog Timer (WD) </li></ul></ul><ul><ul><ul><li>16-bit programmable counter </li></ul></ul></ul><ul><ul><ul><li>maximum watchdog period of 256s with a typical slow clock of 32.768kHz </li></ul></ul></ul><ul><ul><li>One Real Time Timer (RTT) </li></ul></ul><ul><ul><ul><li>20-bit free-running counter </li></ul></ul></ul><ul><ul><ul><li>count elapsed seconds </li></ul></ul></ul><ul><ul><ul><ul><li>1s increment with a typical slow clock of 32.768kHz </li></ul></ul></ul></ul><ul><ul><ul><ul><li>count up to 1048576s (12 days) </li></ul></ul></ul></ul><ul><ul><ul><li>Alarm to generate an interrupt </li></ul></ul></ul>System Timer
    31. 31. <ul><li>Features </li></ul><ul><ul><li>Three 16-bit Timer/Counter channels </li></ul></ul><ul><ul><li>Wide range of functions: </li></ul></ul><ul><ul><ul><li>Frequency measurement </li></ul></ul></ul><ul><ul><ul><li>Event counting </li></ul></ul></ul><ul><ul><ul><li>Interval measurement </li></ul></ul></ul><ul><ul><ul><li>Pulse generation </li></ul></ul></ul><ul><ul><ul><li>Delay timing </li></ul></ul></ul><ul><ul><ul><li>Pulse Width Modulation </li></ul></ul></ul><ul><ul><li>Clock inputs </li></ul></ul><ul><ul><ul><li>3 External and 5 Internal </li></ul></ul></ul><ul><ul><li>Two configurable Input/Ouput signals </li></ul></ul><ul><ul><li>Internal interrupt signal </li></ul></ul>Timer/Counter
    32. 32. <ul><li>Features </li></ul><ul><ul><li>Low power consumption </li></ul></ul><ul><ul><li>Complete time of day clock </li></ul></ul><ul><ul><li>Programmable periodic interrupts </li></ul></ul><ul><ul><li>Alarm </li></ul></ul><ul><ul><ul><li>Five programmable fields: Month, Date, Sec, Min and Hour </li></ul></ul></ul><ul><ul><li>Y2K compliant </li></ul></ul><ul><ul><ul><li>BCD Format </li></ul></ul></ul>Real Time Clock
    33. 33. Ethernet MAC <ul><li>Features </li></ul><ul><ul><li>Compatible with IEEE Standard 802.3 </li></ul></ul><ul><ul><li>10 and 100 Mbits per Second Data Throughput Capability </li></ul></ul><ul><ul><li>MII or RMII Interface to the Physical Layer </li></ul></ul><ul><ul><li>Register Interface to Address, Status and Control Registers </li></ul></ul><ul><ul><li>DMA Interface </li></ul></ul><ul><ul><li>Interrupt Generation to Signal Receive and Transmit Completion </li></ul></ul><ul><ul><li>28-byte Transmit and 28-byte Receive FIFOs </li></ul></ul><ul><ul><li>Automatic Pad and CRC Generation on Transmitted Frames </li></ul></ul><ul><ul><li>Address Checking Logic to Recognize Four 48-bit Addresses </li></ul></ul><ul><ul><li>Supports Promiscuous Mode Where All Valid Frames are Copied to Memory </li></ul></ul><ul><ul><li>Supports Physical Layer Management through MDIO Interface </li></ul></ul>
    34. 34. USB Overview <ul><li>USB is a master/slave protocol </li></ul><ul><ul><li>Host side is complex ( 3 standards: UHCI, OHCI, EHCI) </li></ul></ul><ul><ul><li>Device side is supposed to be easy </li></ul></ul><ul><li>In the embedded world some hosts (mini-hosts) only support some kind of devices (ex. AT43xxx). </li></ul><ul><li>Class drivers is a part of the USB success story: most common devices can be plugged without specific drivers. </li></ul><ul><li>USB 2.0 specification supercedes USB 1.1 specification </li></ul><ul><ul><li>USB 2.0 LS (  USB1.1 at 1.5Mbps) </li></ul></ul><ul><ul><li>USB 2.0 FS (  USB 1.1 at 12Mbps) </li></ul></ul><ul><ul><li>USB 2.0 HS (480 Mbps) </li></ul></ul>
    35. 35. USB Host Port <ul><li>AT91RM9200 embeds a full OHCI Host controller </li></ul><ul><ul><li>All OHCI drivers can run on the AT91RM9200 </li></ul></ul><ul><ul><li>Very difficult to program in a standalone application </li></ul></ul><ul><li>AT91RM9200 OHCI host controller integrates a root hub with 2 downstream ports. </li></ul><ul><ul><li>Port transceiver are embedded in the AT91RM9200 </li></ul></ul><ul><ul><li>VBUS is provided by the PCB </li></ul></ul><ul><ul><li>Discrete components around the USB port are limited to few resistors, no external transceivers </li></ul></ul><ul><li>AT91RM9200 OHCI host controller is one of the 4 ASB bus masters. </li></ul><ul><ul><li>Internal FIFOS warranty the bus latency and the AT91RM9200 has no external master which can hold the bus for a long time </li></ul></ul><ul><ul><li>The 12Mbps can be reached </li></ul></ul>
    36. 36. USB Host Software Stacks <ul><li>Linux and WIN CE provides </li></ul><ul><ul><li>OHCI HCD driver </li></ul></ul><ul><ul><li>USBD Driver </li></ul></ul><ul><ul><li>Main class drivers: Hub, HID, Mass storage, Printer, … </li></ul></ul><ul><li>Symbian and RTOS does not provides USB host stack driver </li></ul><ul><li>SW Ips provider are able to provide solutions for RTOS </li></ul><ul><ul><li>Softconnex, Philog, … </li></ul></ul><ul><li>It is still possible to build a mini host from our full host: </li></ul>Host Controller regs Host Controller Driver (HCD) OHCI-UHCI-EHCI USB Protocol Driver API MS HUB Etc… HID
    37. 37. AT91RM9200 HC existing SW solutions <ul><li>Linux solutions are available and integrated in the linux-2.4.21-rmk1 kernel </li></ul><ul><ul><li>USB mouse or flash disk examples on the CDROM </li></ul></ul><ul><li>WinCE solutions are existing but have not been tested/integrated by the AT91 SW application group </li></ul><ul><ul><li>Refer to Adeset </li></ul></ul><ul><li>Softconnex solutions (USBLink) are exhaustive and reliable </li></ul><ul><ul><li>The stack is available with the Integrity demo </li></ul></ul><ul><ul><li>The AT91 SW application group validate the HC with UBSLink + Nucleus </li></ul></ul><ul><li>Philog has developed a solution for one of the AT91RM9200 lead customer. </li></ul>
    38. 38. USB Device Port <ul><li>When a new device is plugged to a host, the host enumerates the device and automatically looks for a device driver. (Plug and Play) </li></ul><ul><li>2 needs => 2 philosophies </li></ul><ul><ul><li>The device belongs to a standard class driver: HID. Mass storage. In this case, no needs from a custom driver on the host but device firmware is more difficult. </li></ul></ul><ul><ul><li>The device defines its own protocol. In this case, a custom driver must be developed on the host side (PC driver). This could be a very difficult task but the device firmware can be very easy. </li></ul></ul><ul><li>There is no standard in terms of HW for the device. There is no existing standard solutions in Linux or WinCE. </li></ul>
    39. 39. AT91RM9200 USB Device Port <ul><li>USB transceiver embedded: no need of external companion chip </li></ul><ul><li>USB 2.0 full speed compliant (12 Mbps) </li></ul><ul><ul><li>A FIFO is associated with each endpoint </li></ul></ul><ul><ul><li>No DMA, packets can not be corrupted by the ASB bus latency </li></ul></ul><ul><ul><li>Two data banks per endpoint => ping-pong </li></ul></ul>
    40. 40. AT91RM9200 USB Device Port <ul><li>AT91RM9200 USB device configuration </li></ul><ul><ul><li>EP0: 8 bytes control transfers </li></ul></ul><ul><ul><li>EP1, EP2: 64 bytes bulk + ISO + Interrrupt transfers </li></ul></ul><ul><ul><li>EP3: 8 bytes bulk + ISO + Interrrupt transfers </li></ul></ul><ul><ul><li>EP4, EP5: 256 bytes bulk + ISO + Interrrupt transfers </li></ul></ul>
    41. 41. USB device examples <ul><li>Mass Storage device </li></ul><ul><ul><li>The device exports one part of its file system </li></ul></ul><ul><ul><li>The host OS (W2k, XP, Linux) will use its default mass storage driver and mount the new disk in its file system </li></ul></ul><ul><ul><li>The device will require: </li></ul></ul><ul><ul><ul><li>A file system with the media driver (SDCard, MMC, …) </li></ul></ul></ul><ul><ul><ul><li>A mass storage driver (Philog, Softconnex, …) </li></ul></ul></ul><ul><ul><ul><li>Nothing is provided for free in the AT91 library </li></ul></ul></ul><ul><ul><ul><li>A negociation is in progress to have a demo from Softconnex… </li></ul></ul></ul><ul><li>USB bulk device </li></ul><ul><ul><li>The device communicates with the host through 2 unidirectional pipes (bulk In and bulk out) </li></ul></ul><ul><ul><li>The host OS will search for a custom driver. </li></ul></ul><ul><ul><li>The device will require: </li></ul></ul><ul><ul><ul><li>A simple application build from the AT91 library samples </li></ul></ul></ul>
    42. 42. <ul><li>Features </li></ul><ul><ul><li>1 to 32-bit Programmable Data Length </li></ul></ul><ul><ul><li>Receiver and Transmitter Parts Able to Operate Synchronously or Independently, Each Part Interfacing with a Data Signal, a Clock Signal and a Frame Synchronization Signal </li></ul></ul><ul><ul><li>Provides Communication with External Devices in Master or Slave Mode: </li></ul></ul><ul><ul><ul><li>CODECs in Master or Slave Modes </li></ul></ul></ul><ul><ul><ul><li>DAC through Dedicated Serial Interface, Particularly the I2S </li></ul></ul></ul><ul><ul><ul><li>Time Division Multiplexed Buses </li></ul></ul></ul><ul><ul><ul><li>Magnetic Card Reader </li></ul></ul></ul><ul><ul><ul><li>Printer and Scanner Interface </li></ul></ul></ul><ul><ul><ul><li>SPI Used in Full or Half Duplex, in Master or Slave Modes with One Chip Select Only </li></ul></ul></ul>Serial Synchronous Controller
    43. 43. <ul><li>Audio Application </li></ul>Serial Synchronous Controller
    44. 44. <ul><li>Codec Application </li></ul>Serial Synchronous Controller
    45. 45. <ul><li>Time Slot Application </li></ul>Serial Synchronous Controller