part2-2.ppt

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part2-2.ppt

  1. 1. Section 2: Processing Unit
  2. 2. Overview <ul><li>Microprocessor/Microcontrollers </li></ul><ul><li>Digital Signal Processing Processor </li></ul><ul><li>DSP Cores </li></ul><ul><li>Time Processing Units </li></ul>
  3. 3. Good System in General? <ul><li>Fast </li></ul><ul><li>Inexpensive </li></ul><ul><li>Reliable </li></ul><ul><li>Low Power (Portable) </li></ul><ul><li>Quiet </li></ul><ul><li>Light (Portable) </li></ul><ul><li>Durable </li></ul><ul><li>Small </li></ul><ul><li>Expandable </li></ul><ul><li>Software compatibility </li></ul>
  4. 4. Today’s Embedded Processors [Retargetable Compilers for Embedded Core Processor by C. Liem]
  5. 5. Microprocessors & Microcontroller <ul><li>Originally designed for general purpose computing </li></ul><ul><li>Microcontroller = One-chip solution </li></ul><ul><ul><li>CPU </li></ul></ul><ul><ul><li>RAM </li></ul></ul><ul><ul><li>EPROM/ROM </li></ul></ul><ul><ul><li>Serial & parallel I/O </li></ul></ul><ul><ul><li>Timers and various controllers </li></ul></ul><ul><li>Advantage </li></ul><ul><ul><li>Flexible, verified, off-the-shelf </li></ul></ul><ul><li>Popular microcontroller/microprocessors </li></ul><ul><ul><li>Motorola 6800/68000 series (6805, 68hc11, 683xx) </li></ul></ul><ul><ul><li>Intel 80xx/80x86 series (8051, 80?86, i960) </li></ul></ul><ul><ul><li>TMS370 (TI), COP series (Nat’l Semiconductor) etc. </li></ul></ul>
  6. 6. Instruction Architecture <ul><li>RISC (e.g. MIPS) </li></ul><ul><ul><li>simple instruction format </li></ul></ul><ul><ul><ul><li>e.g. MIPS: I,J,R type </li></ul></ul></ul><ul><ul><li>small instruction set </li></ul></ul><ul><ul><li>regular instruction timing </li></ul></ul><ul><ul><ul><li>easy for pipelining </li></ul></ul></ul><ul><ul><li>large register file </li></ul></ul><ul><ul><li>load/store architecture </li></ul></ul><ul><ul><li>overall simple architecture </li></ul></ul><ul><li>VLIW </li></ul><ul><li>Superscaler </li></ul><ul><li>CISC (e.g. 68000) </li></ul><ul><ul><li>variable instruction format </li></ul></ul><ul><ul><li>various instruction size </li></ul></ul><ul><ul><li>data dependent decoding </li></ul></ul><ul><ul><li>irregular instruction timing </li></ul></ul><ul><ul><li>many addressing modes </li></ul></ul><ul><li>SISC (ASIP) </li></ul><ul><ul><li>Specific Instruction Set computer </li></ul></ul><ul><li>Harvard Architecture </li></ul><ul><ul><li>separate data/instruction bus </li></ul></ul>
  7. 7. DSP Processor [DSP Processor Fundamentals by Lapsley etc.]
  8. 8. DSP Processors: Typical Application [DSP Processor Fundamentals by Lapsley etc.]
  9. 9. Common Features of DSP Processors [DSP Processor Fundamentals by Lapsley etc.]
  10. 10. Commercial DSP Processors [DSP Processor Fundamentals by Lapsley etc.]
  11. 11. DSP Cores (ASICs) [DSP Processor Fundamentals by Lapsley etc.]
  12. 12. Common Features of DSP cores <ul><li>Performs dedicated function </li></ul><ul><li>Very strict real-time requirement </li></ul><ul><li>Correctness is essential due to the impact on the surrounding environment </li></ul>
  13. 13. Commercial DSP Cores
  14. 14. Timer Application in Embedded Systems <ul><li>Real-Time clock </li></ul><ul><ul><li>generates an interrupt at periodic intervals </li></ul></ul><ul><ul><li>used by OS to switch between tasks </li></ul></ul><ul><ul><li>update a record of the time of day </li></ul></ul><ul><li>Square-Wave Generator </li></ul><ul><li>Interrupt after Timeout </li></ul><ul><ul><li>watchdog timer </li></ul></ul><ul><li>Elapsed Time Measurement </li></ul>
  15. 15. 68332 Time Processing Unit <ul><li>An intelligent, semi-autonomous micro-controller designed for timing control </li></ul><ul><li>Functions </li></ul><ul><ul><li>Schedules tasks (Scheduler, 3 priorities) </li></ul></ul><ul><ul><li>Processes ROM instructions (Control Store for built-in functions) </li></ul></ul><ul><ul><li>Accesses shared data w/ the CPU (Control Reg, and Para. Ram) </li></ul></ul><ul><ul><li>Performs input and output </li></ul></ul><ul><li>Features </li></ul><ul><ul><li>16 independent, programmable, orthogonal channels </li></ul></ul><ul><ul><li>Interchannel communication </li></ul></ul><ul><ul><li>2 prescaler registers (System-clock or external clock time base) </li></ul></ul><ul><ul><li>Many factory programmed time functions </li></ul></ul><ul><ul><li>Programmable channel priority </li></ul></ul><ul><ul><li>Emulation support </li></ul></ul>
  16. 16. TPU Block Diagram prescaler Select/Initialize channel/function Priority-based (H/M/L) schedule Microprogram for built-in function Intermodule Bus
  17. 17. Built-in Functions <ul><li>Period/Pulse-Width Accumulator </li></ul><ul><li>Output Compare </li></ul><ul><li>Input Capture/Input Transition Count </li></ul><ul><li>Discrete Input/Output (16 bit) </li></ul><ul><li>Pulse Width Modulation </li></ul><ul><li>Period Measurement </li></ul><ul><li>Stepper Motor Control </li></ul><ul><li>and more... </li></ul>
  18. 18. Section 3: Memory
  19. 19. Overview <ul><li>Taxonomy </li></ul><ul><li>SRAM vs. DRAM </li></ul><ul><li>ROM, EPROM, EEPROM, and FLASH Memory </li></ul>
  20. 20. Memory Taxonomy <ul><li>RAM vs. ROM </li></ul><ul><ul><li>READ/WRITE Random Access Memory: SRAM, DRAM </li></ul></ul><ul><ul><li>(Programmable) Read Only Memory: ROM, EPROM, EEPROM </li></ul></ul><ul><li>Static vs. Dynamic </li></ul><ul><ul><li>Static: SRAM, PROM </li></ul></ul><ul><ul><li>Dynamic: DRAM </li></ul></ul><ul><li>Synchronous vs. Asynchronous </li></ul><ul><ul><li>SRAM: Writeback vs. Pipeline Burst or Synchronous Burst </li></ul></ul><ul><ul><li>DRAM: FPM or EDO vs. SDRAM </li></ul></ul><ul><li>Volatile vs. Nonvolatile </li></ul><ul><ul><li>Volatile: Normal RAMs </li></ul></ul><ul><ul><li>Nonvolatile: ROM, EPROM, Battery-backed CMOS </li></ul></ul>
  21. 21. SRAM - 6T design Read : Data/Data* precharged to V cc Assert Row Address Write: Place data on Data/Data* Assert Row Address Complimentary design: very little static power consumption 6 transistor for 1 bit of information Flip/Flop
  22. 22. Static RAM <ul><li>6T design (vs. 4T design) </li></ul><ul><ul><li>Pros </li></ul></ul><ul><ul><ul><li>high speed </li></ul></ul></ul><ul><ul><ul><li>low Power </li></ul></ul></ul><ul><ul><ul><li>better noise immunity </li></ul></ul></ul><ul><ul><li>Cons </li></ul></ul><ul><ul><ul><li>larger area </li></ul></ul></ul><ul><li>Synchronous (vs. Async) </li></ul><ul><ul><li>high performance </li></ul></ul><ul><ul><li>synchronous burst </li></ul></ul><ul><ul><li>pipeline burst </li></ul></ul><ul><li>Nonvolatile </li></ul><ul><ul><li>battery backed-up </li></ul></ul><ul><ul><li>CMOS (BIOS) memory </li></ul></ul>
  23. 23. SRAM vs. DRAM <ul><li>SRAM </li></ul><ul><ul><li><10ns </li></ul></ul><ul><ul><li>cache/CMOS </li></ul></ul><ul><ul><li>4T/6T </li></ul></ul><ul><ul><li>4 x larger than DRAM </li></ul></ul><ul><ul><li>volatile or nonvolatile </li></ul></ul><ul><ul><li>asynchronous or synchronous </li></ul></ul><ul><ul><ul><li>Async: WB, WT </li></ul></ul></ul><ul><ul><ul><li>Sync: Sync. Burst, PB </li></ul></ul></ul><ul><ul><li>Packaging </li></ul></ul><ul><ul><ul><li>On-Chip or DIP </li></ul></ul></ul><ul><ul><li>Typical (cache) size </li></ul></ul><ul><ul><ul><li>Internal: 16KB+16KB (or 32K) </li></ul></ul></ul><ul><ul><ul><li>External: 256-512KB </li></ul></ul></ul><ul><ul><li>Simple interface (easier to use) </li></ul></ul><ul><ul><li>10 x more expensive than DRAM </li></ul></ul><ul><li>DRAM </li></ul><ul><ul><li>60ns-80ns </li></ul></ul><ul><ul><li>main memory </li></ul></ul><ul><ul><li>1T & 1C/3T </li></ul></ul><ul><ul><li>requires refresh logic </li></ul></ul><ul><ul><li>row/column multiplexed access </li></ul></ul><ul><ul><li>volatile </li></ul></ul><ul><ul><li>asynchronous or synchronous </li></ul></ul><ul><ul><ul><li>Async: EDO, FPM, BEDO </li></ul></ul></ul><ul><ul><ul><li>Sync: SDRAM </li></ul></ul></ul><ul><ul><li>Packaging </li></ul></ul><ul><ul><ul><li>SIMM, SIPP, DIMM </li></ul></ul></ul><ul><ul><li>Typical size </li></ul></ul><ul><ul><ul><li>32-64MB </li></ul></ul></ul><ul><ul><ul><li>upto 1GB </li></ul></ul></ul><ul><ul><li>Very complex interface </li></ul></ul>
  24. 24. RAM Configuration N x M ( N : # of locations, M : # of bits per location) 1Mx16-bit memory organization w/ 1Mx8-bit chips
  25. 25. RAM Configuration (cont’d) 4M-wordsx16-bits w/ 4Mx1 chips 4M-wordsx16-bits w/ 512Kx8 chips
  26. 26. CMOS Memory <ul><li>CMOS (Complementary MOS) </li></ul><ul><ul><li>Normal implementation technology of today’s memory </li></ul></ul><ul><ul><li>Main advantage: low power (very small static power dissipation) </li></ul></ul><ul><ul><li>Most power consumption: dynamic power consumption </li></ul></ul><ul><ul><ul><li>dynamic power: (C: capacitance, f:switching, V: power supply) </li></ul></ul></ul><ul><ul><li>Small static power consumption makes it possible to operate CMOS memory from small batteries when the main power is off . </li></ul></ul><ul><li>Standby mode </li></ul><ul><ul><li>Power consumption: 0.1 mW (200mW for active R/W) </li></ul></ul><ul><ul><li>Vcc is reduced (from 5V) to no less than 2.0V & proper CS control </li></ul></ul>
  27. 27. EPROM (Erasable & Programmable ROM) <ul><li>Non-volatile </li></ul><ul><li>Can be programmed and reprogrammed by user </li></ul><ul><li>Invariably byte-organized ( N x8) </li></ul><ul><li>Mainly found in </li></ul><ul><ul><li>embedded system where firmware is held. </li></ul></ul><ul><ul><li>palmtop where OS and system software are held </li></ul></ul><ul><ul><li>bootstrap loader </li></ul></ul>floating gate
  28. 28. EPROM (cont’d) <ul><li>Characteristics </li></ul><ul><ul><li>floating gate: enables non-volatility </li></ul></ul><ul><ul><li>UV-light exposure for erasing (several min) </li></ul></ul><ul><ul><li>Re-programming takes about 5-10 sec/word (EPROM programmer) w/ V pp =10-20V </li></ul></ul><ul><ul><li>Access time: about 100ns </li></ul></ul><ul><ul><li>Low cost and small cell size (20 m 2 at the 1-Mbit) </li></ul></ul><ul><ul><li>Low endurance: maximum of 1000 erase/program cycle </li></ul></ul><ul><ul><li>Reliability Issue: device thresholds might vary w/ repeated reprogramming </li></ul></ul><ul><ul><li>In summary, extremely simple, and dense. making it possible to fabricate large memory at a low cost (but w/o regular reprogramming) </li></ul></ul>G D S
  29. 29. EEPROM <ul><li>Electrical Erasure procedure </li></ul><ul><li>FLOTOX (Floating-gate tunneling oxide): a modified FG </li></ul><ul><ul><li>Reduced gap between floating gate and channel/drain from 100nm (EPROM) to 10-20nm </li></ul></ul><ul><li>Fowler-Nordheim tunneling </li></ul><ul><ul><li>When a voltage of approximately 10V is applied over the thin insulator, electrons travel to and from the floating gate by a mechanism called Fowler-Nordheim tunneling. </li></ul></ul><ul><li>Reversible process </li></ul><ul><ul><li>Erasing is simply achieved by reversing the voltage applied during the writing process. </li></ul></ul><ul><ul><li>may pose the problem of threshold control </li></ul></ul><ul><li>Cons: Larger, high expense, difficult fabrication than EPROM </li></ul><ul><li>Pros: Versatile (10 5 erase/write cycles) </li></ul>
  30. 30. Flash EEPROM <ul><li>Technically, a combination of EPROM & EEPROM </li></ul><ul><ul><li>Programming: avalanche hot-electron-injection </li></ul></ul><ul><ul><li>Erasure: Fowler-Nordheim tunneling </li></ul></ul><ul><ul><li>Difference </li></ul></ul><ul><ul><ul><li>erasure is performed in bulk for the complete chip, or for a subsection of the memory - removal of extra transistor in EEPROM </li></ul></ul></ul><ul><li>Simpler cell structure, smaller cell size, high integration density </li></ul><ul><li>Programming & Erasure: 12V internally generated </li></ul>
  31. 31. EPROM vs. EEPROM vs. Flash EEPROM [Jan Rabaey: Digital Integrated Circuits]

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