Nios II Processor Architecture and  Programming  CEG 4131 Computer Architecture III Miodrag Bolic
Presentation Outline <ul><li>Basic description of Stratix Altera Devices </li></ul><ul><li>NIOS II processor architecture ...
Stratix EP1S10 [2]
 
 
TriMatrix™ Memory [1] M512 Blocks M4K Blocks M-RAM Dedicated External Memory Interface <ul><li>Look-Up Schemes </li></ul><...
Memory Bandwidth Summary Stratix Device Family  [1] 8,784,720 767 364 9 7,427,520   EP1S80 6,762,528 574 292 6 5,215,104  ...
 
Logic Element (LE) [2] Sync Load & Clear Logic 4-Input LUT Register Control Signals Register Chain Input Register Chain Ou...
Logic Array Blocks (LAB) [2] <ul><li>10 LEs </li></ul><ul><li>Local Interconnect </li></ul><ul><li>LAB-Wide Control Signal...
Presentation Outline <ul><li>Basic description   of Stratix Altera Devices </li></ul><ul><li>NIOS II processor architectur...
 
NIOS II Overview [3] <ul><li>Soft IP Core </li></ul><ul><ul><li>A  soft-core processor  is a microprocessor fully describe...
NIOS II Scalability <ul><li>Powerful multiprocessing systems can be built </li></ul>
NIOS II Processor Core [3]
Implementation <ul><li>The functional units of the Nios II architecture form the foundation for the Nios II instruction se...
Types of Processors
Memory Organization
Instruction and Data Cache <ul><li>Useful for high latency external memories </li></ul><ul><li>Cache is direct mapped </li...
Cache Performance Memory I-Cache D-Cache Normalised  Performance SDRAM No No 40.2% SDRAM No Yes 55.2% SDRAM Yes No 64.3% S...
Tightly Coupled Memory  <ul><li>Fast data buffers  </li></ul><ul><li>Fast sections of code  </li></ul><ul><li>Fast interru...
Pipelining <ul><li>Static branch prediction is implemented using the branch offset direction;  </li></ul><ul><ul><li>a neg...
 
Presentation Outline <ul><li>Basic description   of Stratix Altera Devices </li></ul><ul><li>NIOS II processor architectur...
 
Hardware Abstraction Layer (HAL) [4] <ul><li>Isolates the application software from hardware modifications.  </li></ul><ul...
Layers of HAL API [4] <ul><li>HAL library generatioin: </li></ul><ul><ul><li>SOPC Builder generates a hardware system </li...
Programming NIOS II Processor [4] <ul><li>Programming UART </li></ul><ul><ul><li>Standard Input, Standard Output routines ...
References <ul><li>Altera Corp., Stratix & Stratix II Module 3: Using TriMatrix Memories, 2004 </li></ul><ul><li>Altera Co...
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Nios II Architecture

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  • Each LE’s programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register’s clock and clear control signals.
  • How do we build
  • What is the name of the technique for accessing peripherals?
  • Nios II Architecture

    1. 1. Nios II Processor Architecture and Programming CEG 4131 Computer Architecture III Miodrag Bolic
    2. 2. Presentation Outline <ul><li>Basic description of Stratix Altera Devices </li></ul><ul><li>NIOS II processor architecture </li></ul><ul><ul><li>Review pipelining techniques </li></ul></ul><ul><ul><li>Review memory access techniques </li></ul></ul><ul><li>How to design a system using NIOS II processor </li></ul>
    3. 3. Stratix EP1S10 [2]
    4. 6. TriMatrix™ Memory [1] M512 Blocks M4K Blocks M-RAM Dedicated External Memory Interface <ul><li>Look-Up Schemes </li></ul><ul><li>Packet & Cell Buffering </li></ul><ul><li>Cache </li></ul>More Bits For Larger Memory Buffering More Data Ports for Greater Memory Bandwidth <ul><li>Small FIFOs </li></ul><ul><li>Shift Register </li></ul><ul><li>Rake Receiver Correlator </li></ul><ul><li>FIR Filter Delay Line </li></ul><ul><li>Header / Cell Storage </li></ul><ul><li>Channelized Functions </li></ul><ul><li>ATM cell–packet processing </li></ul><ul><li>Nios Program Memory </li></ul><ul><li>Packet / Data Storage </li></ul><ul><li>Nios Program Memory </li></ul><ul><li>System Cache </li></ul><ul><li>Video Frame Buffers </li></ul><ul><li>Echo Canceller Data Storage </li></ul>512 bits per block + parity 4 Kbits per block + parity 512 Kbits per block + parity
    5. 7. Memory Bandwidth Summary Stratix Device Family [1] 8,784,720 767 364 9 7,427,520 EP1S80 6,762,528 574 292 6 5,215,104 EP1S60 4,384,800 384 183 4 3,423,744 EP1S40 3,750,192 295 171 4 3,317,184 EP1S30 2,894,400 224 138 2 1,944,576 EP1S25 2,096,928 194 82 2 1,669,248 EP1S20 1,245,024 94 60 1 920,448 EP1S10 Maximum Bandwidth (Mbps) M512 Blocks M4K Blocks M-RAM Blocks Total RAM Bits Device
    6. 9. Logic Element (LE) [2] Sync Load & Clear Logic 4-Input LUT Register Control Signals Register Chain Input Register Chain Output LUT Chain Output data1 data2 data3 data4 cin Row, Column & DirectLink Routing Local Routing <ul><li>Note: </li></ul><ul><li>Functional Diagram Only. Please See Datasheet for more Details. </li></ul><ul><li>Addnsum & data1 connected via XOR logic </li></ul>LUT Chain Input Register Feedback addnsub (2) D DATA
    7. 10. Logic Array Blocks (LAB) [2] <ul><li>10 LEs </li></ul><ul><li>Local Interconnect </li></ul><ul><li>LAB-Wide Control Signals </li></ul>4 4 4 4 4 4 4 4 4 4 Control Signals Local Interconnect LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE10 LE9
    8. 11. Presentation Outline <ul><li>Basic description of Stratix Altera Devices </li></ul><ul><li>NIOS II processor architecture </li></ul><ul><ul><li>Review pipelining techniques </li></ul></ul><ul><ul><li>Review memory access techniques </li></ul></ul><ul><li>How to design a system using NIOS II processor </li></ul>
    9. 13. NIOS II Overview [3] <ul><li>Soft IP Core </li></ul><ul><ul><li>A soft-core processor is a microprocessor fully described in software, usually in an HDL, which can be synthesized in programmable hardware, such as FPGAs. </li></ul></ul><ul><li>Reduced Instruction Set Computer (RISC) </li></ul><ul><li>No pipeline, 5 or 6 stages pipeline configurations </li></ul><ul><li>Full 32-bit instruction set, data path, and address space </li></ul><ul><li>32 general-purpose registers </li></ul><ul><li>32 external interrupt sources </li></ul><ul><li>Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals </li></ul><ul><li>Software development environment based on the GNU C/C++ tool chain and Eclipse IDE </li></ul>
    10. 14. NIOS II Scalability <ul><li>Powerful multiprocessing systems can be built </li></ul>
    11. 15. NIOS II Processor Core [3]
    12. 16. Implementation <ul><li>The functional units of the Nios II architecture form the foundation for the Nios II instruction set. </li></ul><ul><li>The Nios II architecture describes an instruction set, not a particular hardware implementation. </li></ul><ul><li>Trade-offs: </li></ul><ul><ul><li>More or less of a feature - amount of instruction cache memory. </li></ul></ul><ul><ul><li>Inclusion or exclusion of a feature - the JTAG debug module. </li></ul></ul><ul><ul><li>Hardware implementation or software emulation - divider </li></ul></ul>
    13. 17. Types of Processors
    14. 18. Memory Organization
    15. 19. Instruction and Data Cache <ul><li>Useful for high latency external memories </li></ul><ul><li>Cache is direct mapped </li></ul><ul><ul><li>Low address bits represent cache line </li></ul></ul><ul><li>Use write-though policy </li></ul><ul><ul><li>Data is written to external memory as well as cache </li></ul></ul><ul><li>Problem </li></ul><ul><ul><li>Instruction cache has 32 bytes per cache line </li></ul></ul><ul><ul><li>We choose cache size of 1024 bytes </li></ul></ul><ul><ul><li>Question : How many bits are needed for the tag </li></ul></ul>
    16. 20. Cache Performance Memory I-Cache D-Cache Normalised Performance SDRAM No No 40.2% SDRAM No Yes 55.2% SDRAM Yes No 64.3% SDRAM Yes Yes 96.4% OnChip No No 100.0% OnChip No Yes 98.0% OnChip Yes No 110.2% OnChip Yes Yes 105.6% Performance relative to on chip RAM with no Cache running dhry.c modified for unbuffered I/O Memory I-Cache D-Cache Normalised Performance SDRAM No No 40.2% SDRAM No Yes 55.2% SDRAM Yes No 64.3% SDRAM Yes Yes 96.4% OnChip No No 100.0% OnChip No Yes 98.0% OnChip Yes No 110.2% OnChip Yes Yes 105.6%
    17. 21. Tightly Coupled Memory <ul><li>Fast data buffers </li></ul><ul><li>Fast sections of code </li></ul><ul><li>Fast interrupt handler </li></ul><ul><li>Critical loop </li></ul><ul><li>Constant access time; guaranteed not to have arbitration delays </li></ul><ul><li>Up to 4 tightly coupled memories </li></ul><ul><li>Software Guidelines </li></ul><ul><ul><li>Software accesses tightly-coupled memory addresses just like any other addresses. </li></ul></ul><ul><ul><li>Cache operations have no effect when targeting tightly-coupled </li></ul></ul>
    18. 22. Pipelining <ul><li>Static branch prediction is implemented using the branch offset direction; </li></ul><ul><ul><li>a negative offset is predicted as taken </li></ul></ul><ul><ul><li>a positive offset is predicted as not-taken </li></ul></ul>
    19. 24. Presentation Outline <ul><li>Basic description of Stratix Altera Devices </li></ul><ul><li>NIOS II processor architecture </li></ul><ul><ul><li>Review pipelining techniques </li></ul></ul><ul><ul><li>Review memory access techniques </li></ul></ul><ul><li>How to design a system using NIOS II processor </li></ul>
    20. 26. Hardware Abstraction Layer (HAL) [4] <ul><li>Isolates the application software from hardware modifications. </li></ul><ul><li>Applications are device-independent because they abstract information from such systems as: </li></ul><ul><ul><li>Character mode devices: UART core, JTAG UART core, LCD display controller </li></ul></ul><ul><ul><li>Flash memory devices </li></ul></ul><ul><ul><li>Timer devices </li></ul></ul><ul><ul><li>DMA controller core </li></ul></ul><ul><ul><li>Ethernet MAC/PHY Controller </li></ul></ul><ul><li>HAL application program interface (API) is integrated with the ANSI C standard library. </li></ul>
    21. 27. Layers of HAL API [4] <ul><li>HAL library generatioin: </li></ul><ul><ul><li>SOPC Builder generates a hardware system </li></ul></ul><ul><ul><li>Nios II IDE generates a custom HAL system library to match the hardware configuration </li></ul></ul><ul><li>Changes in the hardware configuration automatically propagate to the HAL device driver configuration </li></ul><ul><li>NIOS II is programmed in C </li></ul>
    22. 28. Programming NIOS II Processor [4] <ul><li>Programming UART </li></ul><ul><ul><li>Standard Input, Standard Output routines in C </li></ul></ul><ul><li>--------------------------------------------------- </li></ul><ul><li>#include <stdio.h> </li></ul><ul><li>#include <string.h> </li></ul><ul><li>int main (void) </li></ul><ul><li>{ </li></ul><ul><li>char* msg = “hello world”; </li></ul><ul><li>FILE* fp; </li></ul><ul><li>fp = fopen (“/dev/uart1”, “w”); </li></ul><ul><li>if (fp) </li></ul><ul><li>{ </li></ul><ul><li>fprintf(fp, “%s”,msg); </li></ul><ul><li>fclose (fp); </li></ul><ul><li>} </li></ul><ul><li>return 0; </li></ul><ul><li>} </li></ul><ul><li>--------------------------------------------------- </li></ul>
    23. 29. References <ul><li>Altera Corp., Stratix & Stratix II Module 3: Using TriMatrix Memories, 2004 </li></ul><ul><li>Altera Corp., Stratix Module 2: Logic Structure & MultiTrack Interconnect, 2004. </li></ul><ul><li>Altera Corp., Nios II Processor Reference Handbook , 2005. </li></ul><ul><li>Altera Corp., Nios II Software Developer's Handbook , 2005. </li></ul>

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