NAND Flash Controller IP Core


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NAND Flash Controller IP Core

  1. 1. NAND Flash Controller IP Core Features • Supports 8 Mbytes to 64 Gbytes Overview • Supports NAND flash memories from The Arasan NAND Flash Controller IP Core constitutes a memory subsystem Samsung, Micron, ST-Micro and oth- that supports memory size from 8 MBytes to 64 Gbytes. Applications include ers. portable memory drives, media players, digital cameras, PDAs, digital TVs, digi- • Supports 64 Mbits to 32 Gbits NAND tal camcorders, PCs, etc. flash devices • Maximum 4 memory banks NAND flash memories from Samsung, Toshiba, Hynix, Micron, ST-Micro, and • Maximum 8 memory devices per others are supported. An optional 512-byte Dual Port RAM (DPRAM) can be included to boost the performance of the controller for high memory capacity. bank For applications with low memory capacity, the DPRAM can be excluded, and • 8-bit or 16-bit flash memory data accessing of the NAND flash memory can be carried out through the 8-bit/16- bus bit latches of the NAND flash interface. The controller supports commands • Configurable 256-byte or 2048-byte including cache read, cache program, two-plane copy-back program, lock/ page size unlock block, and boot sequence. • Configurable setup time, hold time, and wait state A wide variety of optional host buses are supported by the Arasan NAND Flash • Supports cache program, cache read Controller. These include the AHB, PCI, SD, PC Card, CardBus, CompactFlash, • Supports protection mode includes Avalon, BVCI, 8051, and custom buses. To enhance memory utility, an optional lock block, lock tight, and unlock ECC provides 1-bit error correction and 2-bit error detection for 512 bytes page • Arasan NAND Flash Filesystem sim- size, and 4-bit error correction and 2-bit error detection for 2 Kbytes page size. plifies memory read/write • Handles bad block management and The Arasan NAND Flash Filesystem converts the complicated tasks of NAND flash memory interfacing to simple memory access. Flash memory read, write, garbage collection garbage collection, bad block management, and other functions are handled • Optional hardware ECC with multi- in the background by the filesystem. Operating system supported by the NAND ple bits error correction and detec- Flash Filesystem includes Linux, WinCE, and WinXP. tion • Optional 300 MHz 32-bit AHB bus The Arasan NAND Flash Controller IP Core is an RTL design in Verilog that • Programmable through AMBA 2.0 implements a NAND Flash Controller on an ASIC, and FPGA. The core includes AHB bus RTL code, test scripts and a test environment for full simulation verifications. • Optional PCI interface • Optional SD memory interface • Optional PC Card interface • Optional CardBus interface NAND Flash Controller IP Core Functional Block Diagram • Optional CompactFlash interface • Optional Avalon interface Bank 0 • Optional BVCI interface • Optional parallel interface SD, PC Card, NAND CardBus, Flash Custom Interface CompactFlash, Bank 1 8051, etc. Dual-port RAM NAND Flash NAND Interface Flash PCI PCI Target Bank 2 NAND Control Flash Registers ECC Bank 3 AHB Bus AHB Slave NAND Flash Copyright 2006 Arasan Chip Systems Inc. Version 1.0
  2. 2. NAND Flash Controller IP Core NAND Flash Interface: Custom Interface: Benefits: The NAND flash interface provides a 8-bit or A custom host interface can be chosen to 16-bit interface to the flash memories. A provide a mass storage capacity of up to 64 • Fully compliant core with total of 4 memory banks and 8 flash memo- Gbytes. The custom interface includes the proven silicon ries per bank is supported. Each memory SD, PC Card, CardBus, CompactFlash, Avalon, • Premier direct support from bank provides up to 8 chip selects signals. BVCI, generic parallel, 8051, and custom Arasan IP core designers The interface supports a maximum of 64 buses. A host connecting to the custom • Easy-to-use industry stan- Gbytes of NAND flash memory. interface controls the operation of the dard test environment NAND Flash Controller through the NAND • Unencrypted source code Flash Control Registers. Read/write opera- allows easy implementation AHB/APB Interface: tions of the flash memory can be performed The AHB/APB slave block consists of the • Customer training available through the DPRAM or NAND flash inter- • ReUse Methodology Man- Operational registers. An ARM processor face. connecting to the custom interface controls ual guidelines (RMM) com- the operation of the NAND Flash Controller pliant verilog code ensured through the NAND Flash Control Registers. Control Registers: using Spyglass Read/write operations of the flash memory The host processor controls the configura- can be performed through the DPRAM or tion and operation of the NAND Flash Con- NAND flash interface. troller through the Control Registers. Deliverables: Configuration includes the setting of hold • RMM Compliant Synthesiz- time, setup time, wait state, memory config- able RTL design in Verilog PCI Interface: uration, etc. The Control Registers also pro- • Easy-to-use test environment A PCI target interface can be chosen to pro- vide operating status such as Busy and Data • Synthesis scripts vide a mass storage capacity of up to 64 Ready signals. • Technical documents Gbytes. The PCI interface is a fully PCI 2.2 compliant 32-bit, 33/66MHz interface. It also • Sampled device drivers compliant with the PCI Bus Power Manage- NAND Flash Filesystem: ment Interface Specifications revision 1.1. A The Arasan NAND Flash Filesystem provides PCI host controls the operation of the NAND a simple memory accessing interface to Flash Controller through the NAND Flash Linux, WinCE, or WinXP operating systems. Control Registers. Read/write operations of The filesystem handles detail flash memory Optional Items: the flash memory can be performed accessing cycles, bad block registration and management, garbage collections, spare • Arasan NAND Flash Filesys- through the DPRAM or NAND flash inter- memory configuration, memory lock/unlock, tem face. and other flash memory functions. Supported Platforms/Simulators: • Platforms: Solaris, Unix, Linux, WinCE, and Win XP • Verilog simulators: Synopsys Arasan NAND Flash Filesystem VCS, Cadence NC-Verilog, The filesystem simplifies flash memory MTI ModelSim-Verilog accessing and provides functions such as the garbage collection, and bad block management. Arasan Chip Systems, Inc. Data Sheet Links: 1150 N. First St. Suite #210 NAND Flash Controller IP Core Data Sheet: San Jose CA 95112 Phone: 408-282-1600 Fax: 408-282-7800 For a complete directory of Arasan IPs, please Copyright 2006 Arasan Chip Systems Inc. E-mail: visit: