ECE 353 Introduction to Microprocessor Systems Michael J. Schulte Week 8
Topics <ul><li>80C188 system design </li></ul><ul><li>Peripheral Control Block (PCB) </li></ul><ul><li>Characteristics of ...
80C188EB System Design <ul><li>Minimum-component system </li></ul><ul><ul><li>PSD9XXF </li></ul></ul><ul><li>Single and mu...
Peripheral Control Block (PCB) <ul><li>Configuration, control and operation of the 80C188EB’s integrated peripherals </li>...
Memory Subsystems <ul><li>ROM </li></ul><ul><ul><li>Masked </li></ul></ul><ul><ul><li>OTP PROM </li></ul></ul><ul><ul><li>...
Memory Organization <ul><li>Logical organization </li></ul><ul><ul><li>Organization as seen looking at the device from the...
SRAM Interfaces <ul><li>RAM with 3 control inputs </li></ul><ul><ul><li>/CS, /OE, /WE </li></ul></ul><ul><ul><li>Read </li...
SRAM Organization <ul><li>Logical Organization </li></ul><ul><ul><li>Typically 1, 4 , 8 or 16 bit widths </li></ul></ul><u...
EPROM <ul><li>Electrically programmable, non-volatile </li></ul><ul><li>Requires UV light to erase </li></ul><ul><ul><li>Q...
Flash Memory <ul><li>Actually Flash EEPROM, commonly just called flash memory </li></ul><ul><li>Characteristics </li></ul>...
Memory Subsystem Design <ul><li>Memory banks  </li></ul><ul><ul><li>Increasing memory width </li></ul></ul><ul><ul><li>Inc...
Memory Subsystems Review <ul><li>What is the purpose of an address decoder circuit, and where does its output usually get ...
80C186EB Memory Subsystem <ul><li>Organization </li></ul><ul><ul><li>Logical </li></ul></ul><ul><ul><li>Physical </li></ul...
Memory Architectures <ul><li>Wide (n-byte) buses </li></ul><ul><ul><li>Addressing effects </li></ul></ul><ul><ul><li>Byte ...
80C188EB Chip Select Unit (CSU) <ul><li>10 programmable chip selects </li></ul><ul><ul><li>/UCS, /LCS </li></ul></ul><ul><...
External Address Decoders <ul><li>SSI/MSI Decoders </li></ul><ul><ul><li>Discrete gates </li></ul></ul><ul><ul><li>1-of-n ...
 
PCB
pcb.inc ;*********************************************** ;**  I80C188  ** ;**  ** ;**  Peripheral Control Block  ** ;**  I...
RELREG
Chip-Select Start Reg
Chip-Select Stop Register - Part 1
Chip-Select Stop Register  - Part 2
Memory Organization
Physical Organization
 
 
JEDEC
Flash Blocks
Flash Memory Application: Disk-on-Key <ul><li>Up to 1GB nonvolatile storage </li></ul><ul><li>No battery or power supply <...
 
PALCE22V10 Organization
PALCE22V10 Macrocell
RAM Read – 3 control signals
RAM Write – 3 control signals
Cypress  PSoC
Increasing Memory Depth
Increasing Memory Width
Increasing Memory Depth & Width
Upcoming SlideShare
Loading in …5
×

Module 4 - Week 2 slides

354 views

Published on

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
354
On SlideShare
0
From Embeds
0
Number of Embeds
2
Actions
Shares
0
Downloads
11
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Module 4 - Week 2 slides

  1. 1. ECE 353 Introduction to Microprocessor Systems Michael J. Schulte Week 8
  2. 2. Topics <ul><li>80C188 system design </li></ul><ul><li>Peripheral Control Block (PCB) </li></ul><ul><li>Characteristics of ROM and RAM ICs </li></ul><ul><li>Organization and operation of typical static RAM, EPROM and flash memory devices </li></ul><ul><li>Memory subsystem design </li></ul><ul><li>Address decoder implementation </li></ul><ul><li>80C188EB Chip-Select Unit (CSU) </li></ul>
  3. 3. 80C188EB System Design <ul><li>Minimum-component system </li></ul><ul><ul><li>PSD9XXF </li></ul></ul><ul><li>Single and multi-board systems </li></ul><ul><ul><li>Custom single board system </li></ul></ul><ul><ul><li>COTS Single Board Computer </li></ul></ul><ul><ul><li>Custom multi-board system </li></ul></ul><ul><ul><li>Multi-board standard bus system </li></ul></ul><ul><ul><li>SoC </li></ul></ul>
  4. 4. Peripheral Control Block (PCB) <ul><li>Configuration, control and operation of the 80C188EB’s integrated peripherals </li></ul><ul><ul><li>Diagram </li></ul></ul><ul><li>128 contiguous word registers </li></ul><ul><ul><li>All PCB transfers are 16-bits over F-bus </li></ul></ul><ul><ul><li>External bus cycles are still run </li></ul></ul><ul><ul><li>At reset, PCB base address = FF00h in I/O </li></ul></ul><ul><li>pcb.inc </li></ul><ul><li>Relocating the PCB </li></ul><ul><ul><li>RELREG </li></ul></ul>
  5. 5. Memory Subsystems <ul><li>ROM </li></ul><ul><ul><li>Masked </li></ul></ul><ul><ul><li>OTP PROM </li></ul></ul><ul><ul><li>EPROM </li></ul></ul><ul><ul><li>EEPROM </li></ul></ul><ul><ul><li>Flash </li></ul></ul><ul><li>RAM </li></ul><ul><ul><li>SRAM </li></ul></ul><ul><ul><li>DRAM </li></ul></ul><ul><ul><li>Pseudo-SRAM </li></ul></ul><ul><ul><li>Flash – non volatile RAM </li></ul></ul>
  6. 6. Memory Organization <ul><li>Logical organization </li></ul><ul><ul><li>Organization as seen looking at the device from the outside </li></ul></ul><ul><ul><li>Linear array of registers (memory locations) </li></ul></ul><ul><li>Physical organization </li></ul><ul><ul><li>Different physical organizations can be used to implement the same logical organization </li></ul></ul><ul><ul><li>Physical organization affects performance and cost </li></ul></ul>
  7. 7. SRAM Interfaces <ul><li>RAM with 3 control inputs </li></ul><ul><ul><li>/CS, /OE, /WE </li></ul></ul><ul><ul><li>Read </li></ul></ul><ul><ul><li>Write </li></ul></ul><ul><li>RAM with 2 control inputs </li></ul><ul><ul><li>/CS, /WE (or R/W) </li></ul></ul>
  8. 8. SRAM Organization <ul><li>Logical Organization </li></ul><ul><ul><li>Typically 1, 4 , 8 or 16 bit widths </li></ul></ul><ul><li>Physical Organization </li></ul><ul><ul><li>Rectangular bit array </li></ul></ul><ul><ul><li>Two-level decoding (row and column) </li></ul></ul><ul><ul><li>Characteristic delays and timing requirements are specified in memory devices datasheet ( Example ) </li></ul></ul><ul><li>NV-SRAM </li></ul><ul><ul><li>Uses an alternate power source to maintain SRAM when system power is off </li></ul></ul><ul><ul><li>Requires logic to switch power sources and prevent spurious writes during power-up/power-down </li></ul></ul>
  9. 9. EPROM <ul><li>Electrically programmable, non-volatile </li></ul><ul><li>Requires UV light to erase </li></ul><ul><ul><li>Quartz window in package </li></ul></ul><ul><li>Floating polysilicon gate avalanche injection MOS transistor (FAMOS) </li></ul><ul><ul><li>Operation </li></ul></ul><ul><li>Programmer loads device out-of-circuit </li></ul><ul><li>OTP EPROMs eliminate quartz window </li></ul><ul><li>EEPROMs are electrically erasable </li></ul><ul><ul><li>Byte-erasable / writeable </li></ul></ul><ul><ul><li>Low-density </li></ul></ul><ul><li>JEDEC Packages </li></ul>
  10. 10. Flash Memory <ul><li>Actually Flash EEPROM, commonly just called flash memory </li></ul><ul><li>Characteristics </li></ul><ul><ul><li>Technologies </li></ul></ul><ul><ul><li>Endurance </li></ul></ul><ul><ul><li>Blocking , programming and erasing </li></ul></ul><ul><li>Applications </li></ul><ul><ul><li>ROM replacement </li></ul></ul><ul><ul><li>GP NV-RAM </li></ul></ul><ul><ul><li>Solid-state disk (flash-disk) Example </li></ul></ul>
  11. 11. Memory Subsystem Design <ul><li>Memory banks </li></ul><ul><ul><li>Increasing memory width </li></ul></ul><ul><ul><li>Increasing memory depth </li></ul></ul><ul><ul><li>Increasing memory width and depth </li></ul></ul><ul><li>Address decoding </li></ul><ul><ul><li>Exhaustive (full) vs. partial decoding </li></ul></ul><ul><ul><li>Granularity </li></ul></ul><ul><ul><li>Boundaries </li></ul></ul><ul><ul><ul><li>If an address is a 2 n boundary, then what is the result of (address AND (2 n -1))? </li></ul></ul></ul>
  12. 12. Memory Subsystems Review <ul><li>What is the purpose of an address decoder circuit, and where does its output usually get connected? </li></ul><ul><li>What is exhaustive decoding, and what effects does it have? </li></ul><ul><li>What is partial decoding, and what effects does it have? </li></ul>
  13. 13. 80C186EB Memory Subsystem <ul><li>Organization </li></ul><ul><ul><li>Logical </li></ul></ul><ul><ul><li>Physical </li></ul></ul><ul><li>Word operations </li></ul><ul><ul><li>Aligned words </li></ul></ul><ul><ul><li>Unaligned words </li></ul></ul><ul><li>Byte operations </li></ul><ul><ul><li>80C186EB control signals </li></ul></ul><ul><li>Byte-wide peripherals </li></ul>
  14. 14. Memory Architectures <ul><li>Wide (n-byte) buses </li></ul><ul><ul><li>Addressing effects </li></ul></ul><ul><ul><li>Byte transfer support </li></ul></ul><ul><ul><ul><li>Data lanes </li></ul></ul></ul><ul><ul><ul><li>Control signals </li></ul></ul></ul><ul><li>Bus resizing </li></ul><ul><ul><li>Static </li></ul></ul><ul><ul><li>Configurable </li></ul></ul><ul><ul><li>Dynamic </li></ul></ul>
  15. 15. 80C188EB Chip Select Unit (CSU) <ul><li>10 programmable chip selects </li></ul><ul><ul><li>/UCS, /LCS </li></ul></ul><ul><ul><li>/GCS0 - /GCS7 </li></ul></ul><ul><li>Configuration </li></ul><ul><ul><li>Active address range </li></ul></ul><ul><ul><li>Memory or I/O space </li></ul></ul><ul><ul><li>Wait states </li></ul></ul><ul><ul><li>Enable / disable </li></ul></ul><ul><ul><li>Use or ignore READY </li></ul></ul><ul><li>Programming </li></ul><ul><ul><li>Chip-Select Start Register </li></ul></ul><ul><ul><li>Chip-Select Stop Register </li></ul></ul>
  16. 16. External Address Decoders <ul><li>SSI/MSI Decoders </li></ul><ul><ul><li>Discrete gates </li></ul></ul><ul><ul><li>1-of-n Decoders </li></ul></ul><ul><ul><ul><li>74xx138 </li></ul></ul></ul><ul><ul><li>Partial decoding issues </li></ul></ul><ul><li>PLD Decoders </li></ul><ul><ul><li>PLAs </li></ul></ul><ul><ul><li>PALs </li></ul></ul><ul><ul><ul><li>PALCE22V10 </li></ul></ul></ul>
  17. 18. PCB
  18. 19. pcb.inc ;*********************************************** ;** I80C188 ** ;** ** ;** Peripheral Control Block ** ;** Include File for ** ;** I/O Mapping ** ;** ** ;*********************************************** PCBB EQU 0FF00H ; PCB Base Address ;Register Address INTRVEC EQU PCBB + 0020H ; Interrupt Vector Register INTRMSK EQU PCBB + 0028H ; Interrupt Mask Register PRIRMSK EQU PCBB + 002AH ; Priority Mask Register INSERV EQU PCBB + 002CH ; In-Service Register
  19. 20. RELREG
  20. 21. Chip-Select Start Reg
  21. 22. Chip-Select Stop Register - Part 1
  22. 23. Chip-Select Stop Register - Part 2
  23. 24. Memory Organization
  24. 25. Physical Organization
  25. 28. JEDEC
  26. 29. Flash Blocks
  27. 30. Flash Memory Application: Disk-on-Key <ul><li>Up to 1GB nonvolatile storage </li></ul><ul><li>No battery or power supply </li></ul>Specifications: Size: 85x28x15mm (LxWxH) Weight: 17g Data retention up to 10 years Power consumption: Write 36.0mA, Read 33.0mA Erase cycles: 1,000,000 times Read speed > 750KB / sec. Write speed >450 / sec. Shock resistance: 1000 G (maximum)
  28. 32. PALCE22V10 Organization
  29. 33. PALCE22V10 Macrocell
  30. 34. RAM Read – 3 control signals
  31. 35. RAM Write – 3 control signals
  32. 36. Cypress PSoC
  33. 37. Increasing Memory Depth
  34. 38. Increasing Memory Width
  35. 39. Increasing Memory Depth & Width

×